cpu/openc906: Switch to AXI-Lite instead of Wishbone and minor cleanup.
This commit is contained in:
Florent Kermarrec
parent
eebb639c12
commit
1d7aa9c438
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@ -11,7 +11,6 @@ from migen import *
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from litex import get_data_mod
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from litex.soc.interconnect import axi
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
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# Helpers ------------------------------------------------------------------------------------------
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@ -68,8 +67,8 @@ class OpenC906(CPU):
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self.variant = variant
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self.reset = Signal()
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self.interrupt = Signal(240)
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self.wishbone_if = wishbone.Interface(data_width=128, adr_width=36)
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self.periph_buses = [self.wishbone_if] # Peripheral buses (Connected to main SoC's bus).
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self.axi_lite_if = axi.AXILiteInterface(data_width=64, address_width=40)
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self.periph_buses = [self.axi_lite_if] # Peripheral buses (Connected to main SoC's bus).
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self.memory_buses = [] # Memory buses (Connected directly to LiteDRAM).
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# # #
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@ -78,69 +77,69 @@ class OpenC906(CPU):
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cycle_count = Signal(64)
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self.sync += cycle_count.eq(cycle_count + 1)
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# AXI <-> Wishbone conversion.
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axi_if = axi.AXIInterface(data_width=128, address_width=40, id_width=8)
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self.submodules += axi.AXI2Wishbone(axi_if, self.wishbone_if, base_address=0)
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# AXI <-> AXILite conversion.
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axi_if = axi.AXIInterface(data_width=64, address_width=40, id_width=8)
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self.submodules += axi.AXI2AXILite(axi_if, self.axi_lite_if)
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# CPU Instance.
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self.cpu_params = dict(
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# Clk / Rst.
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i_pll_core_cpuclk = ClockSignal("sys"),
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i_pad_cpu_rst_b = ~ResetSignal("sys") | self.reset,
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i_axim_clk_en = 1,
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i_pll_core_cpuclk = ClockSignal("sys"),
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i_pad_cpu_rst_b = ~ResetSignal("sys") | self.reset,
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i_axim_clk_en = 1,
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# Debug (ignored).
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i_sys_apb_clk = 0,
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i_sys_apb_rst_b = 0,
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i_sys_apb_clk = 0,
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i_sys_apb_rst_b = 0,
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# Interrupts
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i_pad_cpu_apb_base = Signal(40, reset=0x9000_0000),
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i_pad_plic_int_cfg = 0,
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i_pad_plic_int_vld = self.interrupt,
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# Interrupts.
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i_pad_cpu_apb_base = Signal(40, reset=0x9000_0000),
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i_pad_plic_int_cfg = 0,
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i_pad_plic_int_vld = self.interrupt,
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# Integrated timer
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i_pad_cpu_sys_cnt = cycle_count,
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# Integrated timer.
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i_pad_cpu_sys_cnt = cycle_count,
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# AXI
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o_biu_pad_awvalid = axi_if.aw.valid,
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i_pad_biu_awready = axi_if.aw.ready,
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o_biu_pad_awid = axi_if.aw.id,
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o_biu_pad_awaddr = axi_if.aw.addr,
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o_biu_pad_awlen = axi_if.aw.len,
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o_biu_pad_awsize = axi_if.aw.size,
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o_biu_pad_awburst = axi_if.aw.burst,
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o_biu_pad_awlock = axi_if.aw.lock,
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o_biu_pad_awcache = axi_if.aw.cache,
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o_biu_pad_awprot = axi_if.aw.prot,
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# AXI.
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o_biu_pad_awvalid = axi_if.aw.valid,
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i_pad_biu_awready = axi_if.aw.ready,
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o_biu_pad_awid = axi_if.aw.id,
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o_biu_pad_awaddr = axi_if.aw.addr,
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o_biu_pad_awlen = axi_if.aw.len,
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o_biu_pad_awsize = axi_if.aw.size,
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o_biu_pad_awburst = axi_if.aw.burst,
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o_biu_pad_awlock = axi_if.aw.lock,
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o_biu_pad_awcache = axi_if.aw.cache,
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o_biu_pad_awprot = axi_if.aw.prot,
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o_biu_pad_wvalid = axi_if.w.valid,
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i_pad_biu_wready = axi_if.w.ready,
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o_biu_pad_wdata = axi_if.w.data,
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o_biu_pad_wstrb = axi_if.w.strb,
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o_biu_pad_wlast = axi_if.w.last,
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o_biu_pad_wvalid = axi_if.w.valid,
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i_pad_biu_wready = axi_if.w.ready,
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o_biu_pad_wdata = axi_if.w.data,
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o_biu_pad_wstrb = axi_if.w.strb,
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o_biu_pad_wlast = axi_if.w.last,
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i_pad_biu_bvalid = axi_if.b.valid,
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o_biu_pad_bready = axi_if.b.ready,
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i_pad_biu_bid = axi_if.b.id,
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i_pad_biu_bresp = axi_if.b.resp,
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i_pad_biu_bvalid = axi_if.b.valid,
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o_biu_pad_bready = axi_if.b.ready,
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i_pad_biu_bid = axi_if.b.id,
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i_pad_biu_bresp = axi_if.b.resp,
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o_biu_pad_arvalid = axi_if.ar.valid,
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i_pad_biu_arready = axi_if.ar.ready,
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o_biu_pad_arid = axi_if.ar.id,
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o_biu_pad_araddr = axi_if.ar.addr,
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o_biu_pad_arlen = axi_if.ar.len,
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o_biu_pad_arsize = axi_if.ar.size,
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o_biu_pad_arburst = axi_if.ar.burst,
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o_biu_pad_arlock = axi_if.ar.lock,
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o_biu_pad_arcache = axi_if.ar.cache,
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o_biu_pad_arprot = axi_if.ar.prot,
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o_biu_pad_arvalid = axi_if.ar.valid,
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i_pad_biu_arready = axi_if.ar.ready,
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o_biu_pad_arid = axi_if.ar.id,
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o_biu_pad_araddr = axi_if.ar.addr,
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o_biu_pad_arlen = axi_if.ar.len,
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o_biu_pad_arsize = axi_if.ar.size,
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o_biu_pad_arburst = axi_if.ar.burst,
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o_biu_pad_arlock = axi_if.ar.lock,
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o_biu_pad_arcache = axi_if.ar.cache,
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o_biu_pad_arprot = axi_if.ar.prot,
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i_pad_biu_rvalid = axi_if.r.valid,
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o_biu_pad_rready = axi_if.r.ready,
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i_pad_biu_rid = axi_if.r.id,
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i_pad_biu_rdata = axi_if.r.data,
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i_pad_biu_rresp = axi_if.r.resp,
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i_pad_biu_rlast = axi_if.r.last,
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i_pad_biu_rvalid = axi_if.r.valid,
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o_biu_pad_rready = axi_if.r.ready,
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i_pad_biu_rid = axi_if.r.id,
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i_pad_biu_rdata = axi_if.r.data,
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i_pad_biu_rresp = axi_if.r.resp,
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i_pad_biu_rlast = axi_if.r.last,
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)
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# Add Verilog sources.
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