cpu/openc906: Switch to AXI-Lite instead of Wishbone and minor cleanup.

litex/soc/cores/cpu/openc906/core.py

@@ -11,7 +11,6 @@ from migen import *
 
 from litex import get_data_mod
 from litex.soc.interconnect import axi
-from litex.soc.interconnect import wishbone
 from litex.soc.cores.cpu import CPU, CPU_GCC_TRIPLE_RISCV64
 
 # Helpers ------------------------------------------------------------------------------------------
@@ -68,8 +67,8 @@ class OpenC906(CPU):
         self.variant      = variant
         self.reset        = Signal()
         self.interrupt    = Signal(240)
-        self.wishbone_if  = wishbone.Interface(data_width=128, adr_width=36)
-        self.periph_buses = [self.wishbone_if] # Peripheral buses (Connected to main SoC's bus).
+        self.axi_lite_if  = axi.AXILiteInterface(data_width=64, address_width=40)
+        self.periph_buses = [self.axi_lite_if] # Peripheral buses (Connected to main SoC's bus).
         self.memory_buses = []                 # Memory buses (Connected directly to LiteDRAM).
 
         # # #
@@ -78,9 +77,9 @@ class OpenC906(CPU):
         cycle_count = Signal(64)
         self.sync += cycle_count.eq(cycle_count + 1)
 
-        # AXI <-> Wishbone conversion.
-        axi_if = axi.AXIInterface(data_width=128, address_width=40, id_width=8)
-        self.submodules += axi.AXI2Wishbone(axi_if, self.wishbone_if, base_address=0)
+        # AXI <-> AXILite conversion.
+        axi_if = axi.AXIInterface(data_width=64,  address_width=40, id_width=8)
+        self.submodules += axi.AXI2AXILite(axi_if, self.axi_lite_if)
 
         # CPU Instance.
         self.cpu_params = dict(
@@ -93,15 +92,15 @@ class OpenC906(CPU):
             i_sys_apb_clk      = 0,
             i_sys_apb_rst_b    = 0,
 
-            # Interrupts
+            # Interrupts.
             i_pad_cpu_apb_base = Signal(40, reset=0x9000_0000),
             i_pad_plic_int_cfg = 0,
             i_pad_plic_int_vld = self.interrupt,
 
-            # Integrated timer
+            # Integrated timer.
             i_pad_cpu_sys_cnt  = cycle_count,
 
-            # AXI
+            # AXI.
             o_biu_pad_awvalid  = axi_if.aw.valid,
             i_pad_biu_awready  = axi_if.aw.ready,
             o_biu_pad_awid     = axi_if.aw.id,