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litex/build/sim: add tapcfg submodule for ethernet
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[submodule "litex/soc/cores/cpu/picorv32/verilog"]
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path = litex/soc/cores/cpu/picorv32/verilog
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url = https://github.com/cliffordwolf/picorv32
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[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
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path = litex/build/sim/core/modules/ethernet/tapcfg
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url = https://github.com/nizox/tapcfg
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litex/build/sim/core/modules/ethernet/tapcfg
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litex/build/sim/core/modules/ethernet/tapcfg
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Subproject commit 4ce399deedc42a44f2854b29f8d34ebbd5d45872
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