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litex/build/sim: add tapcfg submodule for ethernet

This commit is contained in:
Florent Kermarrec 2017-06-28 16:18:15 +02:00
parent 8510b12e93
commit 1d8298af94
2 changed files with 4 additions and 0 deletions
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3
.gitmodules vendored
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@ -10,3 +10,6 @@
[submodule "litex/soc/cores/cpu/picorv32/verilog"] [submodule "litex/soc/cores/cpu/picorv32/verilog"]
path = litex/soc/cores/cpu/picorv32/verilog path = litex/soc/cores/cpu/picorv32/verilog
url = https://github.com/cliffordwolf/picorv32 url = https://github.com/cliffordwolf/picorv32
[submodule "litex/build/sim/core/modules/ethernet/tapcfg"]
path = litex/build/sim/core/modules/ethernet/tapcfg
url = https://github.com/nizox/tapcfg

1
litex/build/sim/core/modules/ethernet/tapcfg Submodule

@ -0,0 +1 @@
Subproject commit 4ce399deedc42a44f2854b29f8d34ebbd5d45872