Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Update .gitmodules 

http to https
This commit is contained in:
atommann 2019-08-12 22:20:34 +08:00 committed by GitHub
parent 2b815f7096
commit 1d957d7a31
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
.gitmodules vendored
View File

@ -18,7 +18,7 @@
url = https://github.com/enjoy-digital/VexRiscv-verilog.git
[submodule "litex/soc/cores/cpu/minerva/verilog"]
path = litex/soc/cores/cpu/minerva/verilog
url = http://github.com/enjoy-digital/minerva-verilog
url = https://github.com/enjoy-digital/minerva-verilog
[submodule "litex/soc/cores/cpu/rocket/verilog"]
path = litex/soc/cores/cpu/rocket/verilog
url = https://github.com/enjoy-digital/rocket-litex-verilog