parent
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@ -18,7 +18,7 @@
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url = https://github.com/enjoy-digital/VexRiscv-verilog.git
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url = https://github.com/enjoy-digital/VexRiscv-verilog.git
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[submodule "litex/soc/cores/cpu/minerva/verilog"]
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[submodule "litex/soc/cores/cpu/minerva/verilog"]
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path = litex/soc/cores/cpu/minerva/verilog
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path = litex/soc/cores/cpu/minerva/verilog
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url = http://github.com/enjoy-digital/minerva-verilog
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url = https://github.com/enjoy-digital/minerva-verilog
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[submodule "litex/soc/cores/cpu/rocket/verilog"]
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[submodule "litex/soc/cores/cpu/rocket/verilog"]
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path = litex/soc/cores/cpu/rocket/verilog
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path = litex/soc/cores/cpu/rocket/verilog
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url = https://github.com/enjoy-digital/rocket-litex-verilog
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url = https://github.com/enjoy-digital/rocket-litex-verilog
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