Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

liteusb: more pep8 (when convenient), should be almost OK

This commit is contained in:
Florent Kermarrec 2015-04-13 14:47:44 +02:00
parent f10e873063
commit 1e1f7ce30e
5 changed files with 14 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
misoclib/com/liteusb/common.py
View File

@ -1,3 +1,5 @@
import random
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.genlib.fsm import * from migen.genlib.fsm import *
from migen.actorlib.fifo import * from migen.actorlib.fifo import *
@ -38,12 +40,10 @@ class LiteUSBTimeout(Module):
) )
self.comb += self.done.eq(cnt == cnt_max) self.comb += self.done.eq(cnt == cnt_max)
# #
# TB # TB
# #
import random
def randn(max_n): def randn(max_n):
return random.randint(0, max_n-1) return random.randint(0, max_n-1)

1
misoclib/com/liteusb/core/crc.py
View File

@ -103,6 +103,7 @@ class CRC32(Module):
polynom = 0x04C11DB7 polynom = 0x04C11DB7
init = 2**width-1 init = 2**width-1
check = 0xC704DD7B check = 0xC704DD7B
def __init__(self, dat_width): def __init__(self, dat_width):
self.d = Signal(dat_width) self.d = Signal(dat_width)
self.value = Signal(self.width) self.value = Signal(self.width)

7
misoclib/com/liteusb/core/depacketizer.py
View File

@ -77,7 +77,9 @@ class LiteUSBDepacketizer(Module):
source.eop.eq(eop), source.eop.eq(eop),
source.d.eq(sink.d), source.d.eq(sink.d),
sink.ack.eq(source.ack), sink.ack.eq(source.ack),
If((eop & sink.stb & source.ack) | self.timeout.done, NextState("WAIT_SOP")) If((eop & sink.stb & source.ack) | self.timeout.done,
NextState("WAIT_SOP")
)
) )
self.sync += \ self.sync += \
@ -94,7 +96,8 @@ class LiteUSBDepacketizer(Module):
# #
src_data = [ src_data = [
0x5A, 0xA5, 0x5A, 0xA5, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x02, 0x03, 0x5A, 0xA5, 0x5A, 0xA5, 0x01, 0x00, 0x00, 0x00, 0x04, 0x00, 0x01, 0x02, 0x03,
0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03, 0x04, 0x05, 0x06, 0x07, 0x5A, 0xA5, 0x5A, 0xA5, 0x12, 0x00, 0x00, 0x00, 0x08, 0x00, 0x01, 0x02, 0x03,
0x04, 0x05, 0x06, 0x07,
]*4 ]*4

2
misoclib/com/liteusb/frontend/uart.py
View File

@ -24,7 +24,7 @@ class LiteUSBUART(Module, AutoCSR):
# TX # TX
tx_start = self._rxtx.re tx_start = self._rxtx.re
tx_done = self.ev.tx.trigger tx_done = self.ev.tx.trigger
self.sync += \ self.sync += \
If(tx_start, If(tx_start,

8
misoclib/com/liteusb/phy/ft2232h.py
View File

@ -68,7 +68,7 @@ class FT2232HPHY(Module):
read_time_en, max_read_time = anti_starvation(read_time) read_time_en, max_read_time = anti_starvation(read_time)
write_time_en, max_write_time = anti_starvation(write_time) write_time_en, max_write_time = anti_starvation(write_time)
data_w_accepted = Signal(reset=1) data_w_accepted = Signal(reset=1)
fsm = FSM() fsm = FSM()
self.submodules += RenameClockDomains(fsm, {"sys": "ftdi"}) self.submodules += RenameClockDomains(fsm, {"sys": "ftdi"})
@ -97,8 +97,8 @@ class FT2232HPHY(Module):
# Read / Write Actions # Read / Write Actions
# #
data_w = Signal(dw) data_w = Signal(dw)
data_r = Signal(dw) data_r = Signal(dw)
data_oe = Signal() data_oe = Signal()
if hasattr(pads, "oe_n"): if hasattr(pads, "oe_n"):
@ -256,7 +256,7 @@ class UserModel(Module, RandRun):
LENGTH = 512 LENGTH = 512
model_rd_data = [i%256 for i in range(LENGTH)][::-1] model_rd_data = [i%256 for i in range(LENGTH)][::-1]
user_wr_data = [i%256 for i in range(LENGTH)] user_wr_data = [i%256 for i in range(LENGTH)]
class TB(Module): class TB(Module):