targets/icebreaker: simplify, use standard VexRiscv, add iCE40PLL and run BIOS from SPI Flash.
This commit is contained in:
Florent Kermarrec
parent
197bdcb026
commit
1e9aa64387
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@ -3,184 +3,123 @@
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# This file is Copyright (c) 2019 Sean Cross <sean@xobs.io>
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# This file is Copyright (c) 2018 David Shah <dave@ds0.me>
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# This file is Copyright (c) 2020 Piotr Esden-Tempski <piotr@esden.net>
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# This file is Copyright (c) 2020 Florent Kermarrec <florent@enjoy-digital.fr>
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# License: BSD
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# This target was originally based on the Fomu target.
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import argparse
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from migen import *
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from migen.genlib.resetsync import AsyncResetSynchronizer
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from litex.soc.cores import up5kspram, spi_flash
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from litex.soc.integration.soc_core import SoCCore
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from litex.soc.integration.builder import Builder, builder_argdict, builder_args
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from litex.soc.integration.soc_core import soc_core_argdict, soc_core_args
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from litex.soc.integration.doc import AutoDoc
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from litex.boards.platforms import icebreaker
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from litex_boards.platforms.icebreaker import Platform
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from litex.soc.cores.up5kspram import Up5kSPRAM
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from litex.soc.cores.spi_flash import SpiFlash
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from litex.soc.cores.clock import iCE40PLL
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from litex.soc.integration.soc_core import *
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from litex.soc.integration.builder import *
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from litex.soc.interconnect import wishbone
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from litex.soc.cores.uart import UARTWishboneBridge
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from litex.soc.cores.gpio import GPIOOut
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class JumpToAddressROM(wishbone.SRAM):
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def __init__(self, size, addr):
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data = [
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0x00000537 | ((addr & 0xfffff000) << 0), # lui a0,%hi(addr)
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0x00052503 | ((addr & 0x00000fff) << 20), # lw a0,%lo(addr)(a0)
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0x000500e7, # jalr a0
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]
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wishbone.SRAM.__init__(self, size, read_only=True, init=data)
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kB = 1024
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mB = 1024*kB
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# CRG ----------------------------------------------------------------------------------------------
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class _CRG(Module):
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def __init__(self, platform):
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def __init__(self, platform, sys_clk_freq):
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self.clock_domains.cd_sys = ClockDomain()
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self.clock_domains.cd_por = ClockDomain()
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self.reset = Signal()
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# # #
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reset_delay = Signal(12, reset=4095)
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# Clocks
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# Clocking
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clk12 = platform.request("clk12")
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platform.add_period_constraint(clk12, 1e9/12e6)
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self.comb += self.cd_sys.clk.eq(clk12)
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self.comb += self.cd_por.clk.eq(clk12)
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self.comb += self.cd_sys.rst.eq(reset_delay != 0)
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rst_n = platform.request("user_btn_n")
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if sys_clk_freq == 12e6:
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self.comb += self.cd_sys.clk.eq(clk12)
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else:
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self.submodules.pll = pll = iCE40PLL(primitive="SB_PLL40_PAD")
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pll.register_clkin(clk12, 12e6)
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pll.create_clkout(self.cd_sys, sys_clk_freq)
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platform.add_period_constraint(self.cd_sys.clk, 1e9/sys_clk_freq)
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# Power On Reset
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self.sync.por += If(reset_delay != 0, reset_delay.eq(reset_delay - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, self.reset)
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por_cycles = 4096
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por_counter = Signal(log2_int(por_cycles), reset=por_cycles-1)
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self.comb += self.cd_por.clk.eq(self.cd_sys.clk)
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platform.add_period_constraint(self.cd_por.clk, 1e9/sys_clk_freq)
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self.sync.por += If(por_counter != 0, por_counter.eq(por_counter - 1))
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self.specials += AsyncResetSynchronizer(self.cd_por, ~rst_n)
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self.specials += AsyncResetSynchronizer(self.cd_sys, (por_counter != 0))
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# BaseSoC ------------------------------------------------------------------------------------------
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class BaseSoC(SoCCore):
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"""A SoC on iCEBreaker, optionally with a softcore CPU"""
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# Statically-define the memory map, to prevent it from shifting across various litex versions.
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SoCCore.mem_map = {
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"rom": 0x00000000, # (default shadow @0x80000000)
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"sram": 0x10000000, # (default shadow @0xa0000000)
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"spiflash": 0x20000000, # (default shadow @0xa0000000)
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"csr": 0xe0000000, # (default shadow @0x60000000)
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"vexriscv_debug": 0xf00f0000,
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"sram": 0x10000000,
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"spiflash": 0x20000000,
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"csr": 0xf0000000,
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}
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def __init__(self, bios_flash_offset, **kwargs):
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sys_clk_freq = int(24e6)
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platform = icebreaker.Platform()
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def __init__(self, debug=True, boot_vector=0x2001a000, **kwargs):
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"""Create a basic SoC for iCEBreaker.
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Create a basic SoC for iCEBreaker. The `sys` frequency will run at 12 MHz.
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Returns:
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Newly-constructed SoC
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"""
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platform = Platform()
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kwargs["cpu_variant"] = "lite"
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kwargs["cpu_reset_address"] = boot_vector
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if debug:
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kwargs["uart_name"] = "crossover"
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kwargs["cpu_variant"] = "lite+debug"
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clk_freq = int(12e6)
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# Force the SRAM size to 0, because we add our own SRAM with SPRAM
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# Disable Integrated ROM/SRAM since too large for iCE40 and UP5K has specific SPRAM.
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kwargs["integrated_sram_size"] = 0
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kwargs["integrated_rom_size"] = 0
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SoCCore.__init__(self, platform, clk_freq, **kwargs)
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# Set CPU variant / reset address
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kwargs["cpu_reset_address"] = self.mem_map["spiflash"] + bios_flash_offset
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# If there is a VexRiscv CPU, add a fake ROM that simply tells the CPU
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# to jump to the given address.
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if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
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self.add_memory_region("rom", 0, 16)
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self.submodules.rom = JumpToAddressROM(16, boot_vector)
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# CRG --------------------------------------------------------------------------------------
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self.submodules.crg = _CRG(platform, sys_clk_freq)
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self.submodules.crg = _CRG(platform)
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# SoCCore ----------------------------------------------------------------------------------
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SoCCore.__init__(self, platform, sys_clk_freq, **kwargs)
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# UP5K has single port RAM, which is a dedicated 128 kilobyte block.
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# Use this as CPU RAM.
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spram_size = 128 * 1024
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self.submodules.spram = up5kspram.Up5kSPRAM(size=spram_size)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, spram_size)
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# 128KB SPRAM (used as SRAM) ---------------------------------------------------------------
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self.submodules.spram = Up5kSPRAM(size=64*kB)
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self.register_mem("sram", self.mem_map["sram"], self.spram.bus, 64*kB)
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# The litex SPI module supports memory-mapped reads, as well as a bit-banged mode
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# for doing writes.
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spi_pads = platform.request("spiflash4x")
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self.submodules.lxspi = spi_flash.SpiFlash(spi_pads, dummy=6, endianness="little")
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self.register_mem("spiflash", self.mem_map["spiflash"], self.lxspi.bus, size=16 * 1024 * 1024)
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self.add_csr("lxspi")
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# SPI Flash --------------------------------------------------------------------------------
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self.submodules.spiflash = SpiFlash(platform.request("spiflash4x"), dummy=6, endianness="little")
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self.register_mem("spiflash", self.mem_map["spiflash"], self.spiflash.bus, size=16*mB)
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self.add_csr("spiflash")
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# In debug mode, add a UART bridge. This takes over from the normal UART bridge,
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# however you can use the "crossover" UART to communicate with this over the bridge.
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if debug:
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self.submodules.uart_bridge = UARTWishboneBridge(platform.request("serial"), clk_freq, baudrate=115200)
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self.add_wb_master(self.uart_bridge.wishbone)
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if hasattr(self, "cpu") and self.cpu.name == "vexriscv":
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self.register_mem("vexriscv_debug", 0xf00f0000, self.cpu.debug_bus, 0x100)
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# Add ROM linker region --------------------------------------------------------------------
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self.add_memory_region("rom", self.mem_map["spiflash"] + bios_flash_offset, 32*kB, type="cached+linker")
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self.submodules.leds = GPIOOut(Cat(
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platform.request("user_ledr_n"),
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platform.request("user_ledg_n")))
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self.add_csr("leds")
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# Leds -------------------------------------------------------------------------------------
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counter = Signal(32)
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self.sync += counter.eq(counter + 1)
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self.comb += platform.request("user_ledr_n").eq(counter[26])
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self.comb += platform.request("user_ledg_n").eq(~counter[26])
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# self.add_memory_region("rom", 0x2001a000, 16 * 1024 * 1024 - 0x1a000, type="cached+linker")
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# self.add_memory_region("boot", 0, 16, type="cached+linker")
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# self.mem_regions["rom"] = SoCMemRegion(0x2001a000, 16 * 1024 * 1024 - 0x1a000, "cached")
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# self.mem_regions["boot"] = SoCMemRegion(0, 16, "cached")
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# Flash --------------------------------------------------------------------------------------------
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def set_yosys_nextpnr_settings(self, nextpnr_seed=0, nextpnr_placer="heap"):
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"""Set Yosys/Nextpnr settings by overriding default LiteX's settings.
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Args:
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nextpnr_seed (int): Seed to use in Nextpnr
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nextpnr_placer (str): Placer to use in Nextpnr
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"""
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assert hasattr(self.platform.toolchain, "yosys_template")
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assert hasattr(self.platform.toolchain, "build_template")
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self.platform.toolchain.yosys_template = [
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"{read_files}",
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"attrmap -tocase keep -imap keep=\"true\" keep=1 -imap keep=\"false\" keep=0 -remove keep=0",
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# Use "-relut -dffe_min_ce_use 4" to the synth_ice40 command. The "-reult" adds an additional
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# LUT pass to pack more stuff in, and the "-dffe_min_ce_use 4" flag prevents Yosys from
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# generating a Clock Enable signal for a LUT that has fewer than 4 flip-flops. This increases
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# density, and lets us use the FPGA more efficiently.
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"synth_ice40 -json {build_name}.json -top {build_name} -relut -abc2 -dffe_min_ce_use 4 -relut",
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]
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self.platform.toolchain.build_template = [
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"yosys -q -l {build_name}.rpt {build_name}.ys",
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"nextpnr-ice40 --json {build_name}.json --pcf {build_name}.pcf --asc {build_name}.txt"
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+ " --pre-pack {build_name}_pre_pack.py --{architecture} --package {package}"
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+ " --seed {}".format(nextpnr_seed)
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+ " --placer {}".format(nextpnr_placer),
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# Disable final deep-sleep power down so firmware words are loaded onto softcore's address bus.
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"icepack -s {build_name}.txt {build_name}.bin"
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]
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def flash(bios_flash_offset):
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from litex.build.lattice.programmer import IceStormProgrammer
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prog = IceStormProgrammer()
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prog.flash(bios_flash_offset, "soc_basesoc_icebreaker/software/bios/bios.bin")
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prog.flash(0x00000000, "soc_basesoc_icebreaker/gateware/top.bin")
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exit()
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# Build --------------------------------------------------------------------------------------------
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def main():
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parser = argparse.ArgumentParser(description="LiteX SoC on iCEBreaker")
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parser.add_argument("--nextpnr-seed", default=0, help="Seed to use in Nextpnr")
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parser.add_argument("--nextpnr-placer", default="heap", choices=["sa", "heap"], help="Placer implementation to use in Nextpnr")
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parser.add_argument("--bios-flash-offset", default=0x40000, help="BIOS offset in SPI Flash")
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parser.add_argument("--flash", action="store_true", help="Load Bitstream")
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builder_args(parser)
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soc_core_args(parser)
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args = parser.parse_args()
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soc = BaseSoC(debug=True, **soc_core_argdict(args))
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soc.set_yosys_nextpnr_settings(nextpnr_seed=args.nextpnr_seed, nextpnr_placer=args.nextpnr_placer)
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if args.flash:
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flash(args.bios_flash_offset)
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# Don't build software -- we don't include it since we just jump to SPI flash.
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builder_kwargs = builder_argdict(args)
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builder_kwargs["compile_software"] = False
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builder = Builder(soc, **builder_kwargs)
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soc = BaseSoC(args.bios_flash_offset, **soc_core_argdict(args))
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builder = Builder(soc, **builder_argdict(args))
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builder.build()
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if __name__ == "__main__":
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main()
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