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soc/add_pcie: Add address_width support for 64-bit addressing.

This commit is contained in:
Florent Kermarrec 2022-03-10 16:09:18 +01:00
parent f446415f68
commit 1ebcc03a92
1 changed files with 11 additions and 4 deletions
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15
litex/soc/integration/soc.py
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@ -1741,7 +1741,7 @@ class LiteXSoC(SoC):
self.sata_phy.crg.cd_sata_rx.clk) self.sata_phy.crg.cd_sata_rx.clk)
# Add PCIe ------------------------------------------------------------------------------------- # Add PCIe -------------------------------------------------------------------------------------
def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, def add_pcie(self, name="pcie", phy=None, ndmas=0, max_pending_requests=8, address_width=32,
with_dma_buffering = True, dma_buffering_depth=1024, with_dma_buffering = True, dma_buffering_depth=1024,
with_dma_loopback = True, with_dma_loopback = True,
with_msi = True): with_msi = True):
@ -1755,7 +1755,11 @@ class LiteXSoC(SoC):
# Endpoint. # Endpoint.
self.check_if_exists(f"{name}_endpoint") self.check_if_exists(f"{name}_endpoint")
endpoint = LitePCIeEndpoint(phy, max_pending_requests=max_pending_requests, endianness=phy.endianness) endpoint = LitePCIeEndpoint(phy,
max_pending_requests = max_pending_requests,
endianness = phy.endianness,
address_width = address_width
)
setattr(self.submodules, f"{name}_endpoint", endpoint) setattr(self.submodules, f"{name}_endpoint", endpoint)
# MMAP. # MMAP.
@ -1778,11 +1782,14 @@ class LiteXSoC(SoC):
self.check_if_exists(f"{name}_dma{i}") self.check_if_exists(f"{name}_dma{i}")
dma = LitePCIeDMA(phy, endpoint, dma = LitePCIeDMA(phy, endpoint,
with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth, with_buffering = with_dma_buffering, buffering_depth=dma_buffering_depth,
with_loopback = with_dma_loopback) with_loopback = with_dma_loopback,
address_width = address_width
)
setattr(self.submodules, f"{name}_dma{i}", dma) setattr(self.submodules, f"{name}_dma{i}", dma)
self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq
self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq
self.add_constant("DMA_CHANNELS", ndmas) self.add_constant("DMA_CHANNELS", ndmas)
self.add_constant("DMA_ADDR_WIDTH", address_width)
# Map/Connect IRQs. # Map/Connect IRQs.
if with_msi: if with_msi: