migen/fhdl/tools: fix rename_clock_domain when new == old

Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
This commit is contained in:
Florent Kermarrec 2015-07-24 12:48:51 +02:00
parent 493f424ebd
commit 1f1ff5a5e9
1 changed files with 7 additions and 6 deletions

View File

@ -256,12 +256,13 @@ def rename_clock_domain_expr(f, old, new):
def rename_clock_domain(f, old, new):
rename_clock_domain_expr(f, old, new)
if old in f.sync:
if new in f.sync:
f.sync[new].extend(f.sync[old])
else:
f.sync[new] = f.sync[old]
del f.sync[old]
if new != old:
if old in f.sync:
if new in f.sync:
f.sync[new].extend(f.sync[old])
else:
f.sync[new] = f.sync[old]
del f.sync[old]
for special in f.specials:
special.rename_clock_domain(old, new)
try: