migen/fhdl/tools: fix rename_clock_domain when new == old
Clock domain renaming should support new == old to allow programmatically determined clock domain renaming.
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@ -256,12 +256,13 @@ def rename_clock_domain_expr(f, old, new):
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def rename_clock_domain(f, old, new):
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def rename_clock_domain(f, old, new):
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rename_clock_domain_expr(f, old, new)
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rename_clock_domain_expr(f, old, new)
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if old in f.sync:
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if new != old:
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if new in f.sync:
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if old in f.sync:
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f.sync[new].extend(f.sync[old])
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if new in f.sync:
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else:
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f.sync[new].extend(f.sync[old])
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f.sync[new] = f.sync[old]
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else:
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del f.sync[old]
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f.sync[new] = f.sync[old]
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del f.sync[old]
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for special in f.specials:
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for special in f.specials:
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special.rename_clock_domain(old, new)
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special.rename_clock_domain(old, new)
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try:
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try:
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