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soc/cores/dma/WishboneDMAReader: Add back endianness swap afer FIFO addition.

This commit is contained in:
Florent Kermarrec 2023-01-10 10:51:13 +01:00
parent 2d7cd7802c
commit 1f2a44516e
1 changed files with 1 additions and 1 deletions
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litex/soc/cores/dma.py
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@ -58,7 +58,7 @@ class WishboneDMAReader(Module, AutoCSR):
bus.sel.eq(2**(bus.data_width//8)-1), bus.sel.eq(2**(bus.data_width//8)-1),
bus.adr.eq(sink.address), bus.adr.eq(sink.address),
fifo.sink.last.eq(sink.last), fifo.sink.last.eq(sink.last),
fifo.sink.data.eq(bus.dat_r), fifo.sink.data.eq(format_bytes(bus.dat_r, endianness)),
If(bus.stb & bus.ack, If(bus.stb & bus.ack,
sink.ready.eq(1), sink.ready.eq(1),
fifo.sink.valid.eq(1), fifo.sink.valid.eq(1),