soc/cores/dma/WishboneDMAReader: Add back endianness swap afer FIFO addition.

2023-01-10 10:51:13 +01:00 · 2023-01-10 10:51:13 +01:00 · 1f2a44516e
parent 2d7cd7802c
commit 1f2a44516e
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/cores/dma.py
+++ b/litex/soc/cores/dma.py
@ -58,7 +58,7 @@ class WishboneDMAReader(Module, AutoCSR):
            bus.sel.eq(2**(bus.data_width//8)-1),
            bus.adr.eq(sink.address),
            fifo.sink.last.eq(sink.last),
-            fifo.sink.data.eq(bus.dat_r),
+            fifo.sink.data.eq(format_bytes(bus.dat_r, endianness)),
            If(bus.stb & bus.ack,
                sink.ready.eq(1),
                fifo.sink.valid.eq(1),