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integration/soc: Switch to LiteXModule and from self.submodules/self.clock_domains to self.

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This commit is contained in:
Florent Kermarrec 2022-10-27 16:03:01 +02:00
parent f8702d744f
commit 1f2d4f017a
1 changed files with 61 additions and 62 deletions
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123
litex/soc/integration/soc.py
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@ -113,7 +113,7 @@ class SoCCSRRegion:
# SoCBusHandler ------------------------------------------------------------------------------------
class SoCBusHandler(Module):
class SoCBusHandler(LiteXModule):
supported_standard = ["wishbone", "axi-lite", "axi"]
supported_data_width = [32, 64]
supported_address_width = [32]
@ -485,7 +485,7 @@ class SoCBusHandler(Module):
# SoCLocHandler ------------------------------------------------------------------------------------
class SoCLocHandler(Module):
class SoCLocHandler(LiteXModule):
# Creation -------------------------------------------------------------------------------------
def __init__(self, name, n_locs):
self.name = name
@ -732,7 +732,7 @@ class SoCIRQHandler(SoCLocHandler):
# SoCController ------------------------------------------------------------------------------------
class SoCController(Module, AutoCSR):
class SoCController(LiteXModule):
def __init__(self, with_reset=True, with_scratch=True, with_errors=True):
if with_reset:
self._reset = CSRStorage(fields=[
@ -808,7 +808,7 @@ class SoC(LiteXModule):
self.csr_regions = {}
# SoC Bus Handler --------------------------------------------------------------------------
self.submodules.bus = SoCBusHandler(
self.bus = SoCBusHandler(
standard = bus_standard,
data_width = bus_data_width,
address_width = bus_address_width,
@ -819,7 +819,7 @@ class SoC(LiteXModule):
)
# SoC Bus Handler --------------------------------------------------------------------------
self.submodules.csr = SoCCSRHandler(
self.csr = SoCCSRHandler(
data_width = csr_data_width,
address_width = csr_address_width,
alignment = 32,
@ -829,7 +829,7 @@ class SoC(LiteXModule):
)
# SoC IRQ Handler --------------------------------------------------------------------------
self.submodules.irq = SoCIRQHandler(
self.irq = SoCIRQHandler(
n_irqs = irq_n_irqs,
reserved_irqs = irq_reserved_irqs
)
@ -891,7 +891,7 @@ class SoC(LiteXModule):
self.logger.info("Controller {} {}.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
setattr(self.submodules, name, SoCController(**kwargs))
setattr(self, name, SoCController(**kwargs))
def add_ram(self, name, origin, size, contents=[], mode="rwx"):
ram_cls = {
@ -916,7 +916,7 @@ class SoC(LiteXModule):
colorer(name),
colorer("added", color="green"),
self.bus.regions[name]))
setattr(self.submodules, name, ram)
setattr(self, name, ram)
if contents != []:
self.add_config(f"{name}_INIT", 1)
@ -951,7 +951,7 @@ class SoC(LiteXModule):
self.logger.info("CSR Bridge {} {}.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
setattr(self.submodules, csr_bridge_name, csr_bridge)
setattr(self, csr_bridge_name, csr_bridge)
csr_size = 2**(self.csr.address_width + 2)
csr_region = SoCRegion(origin=origin, size=csr_size, cached=False, decode=self.cpu.csr_decode)
bus_standard = {
@ -989,7 +989,7 @@ class SoC(LiteXModule):
colorer("\n - ".join(sorted(cpu_cls.variants)))))
raise SoCError()
self.check_if_exists("cpu")
self.submodules.cpu = cpu_cls(self.platform, variant)
self.cpu = cpu_cls(self.platform, variant)
self.logger.info("CPU {} {}.".format(
colorer(name, color="underline"),
colorer("added", color="green")))
@ -1060,7 +1060,7 @@ class SoC(LiteXModule):
self.logger.info("CPU {} {} DMA Bus.".format(
colorer(name, color="underline"),
colorer("adding", color="cyan")))
self.submodules.dma_bus = SoCBusHandler(
self.dma_bus = SoCBusHandler(
name = "SoCDMABusHandler",
standard = "wishbone",
data_width = self.bus.data_width,
@ -1097,7 +1097,7 @@ class SoC(LiteXModule):
def add_timer(self, name="timer0"):
from litex.soc.cores.timer import Timer
self.check_if_exists(name)
setattr(self.submodules, name, Timer())
setattr(self, name, Timer())
if self.irq.enabled:
self.irq.add(name, use_loc_if_exists=True)
@ -1142,7 +1142,7 @@ class SoC(LiteXModule):
if ((len(self.bus.masters) == 1) and
(len(self.bus.slaves) == 1) and
(next(iter(self.bus.regions.values())).origin == 0)):
self.submodules.bus_interconnect = interconnect_p2p_cls(
self.bus_interconnect = interconnect_p2p_cls(
master = next(iter(self.bus.masters.values())),
slave = next(iter(self.bus.slaves.values())))
# Otherwise, use InterconnectShared/Crossbar.
@ -1151,7 +1151,7 @@ class SoC(LiteXModule):
"shared" : interconnect_shared_cls,
"crossbar": interconnect_crossbar_cls,
}[self.bus.interconnect]
self.submodules.bus_interconnect = interconnect_cls(
self.bus_interconnect = interconnect_cls(
masters = list(self.bus.masters.values()),
slaves = [(self.bus.regions[n].decoder(self.bus), s) for n, s in self.bus.slaves.items()],
register = True,
@ -1175,12 +1175,12 @@ class SoC(LiteXModule):
if ((len(self.dma_bus.masters) == 1) and
(len(self.dma_bus.slaves) == 1) and
(next(iter(self.dma_bus.regions.values())).origin == 0)):
self.submodules.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
self.dma_bus_interconnect = wishbone.InterconnectPointToPoint(
master = next(iter(self.dma_bus.masters.values())),
slave = next(iter(self.dma_bus.slaves.values())))
# Otherwise, use InterconnectShared.
else:
self.submodules.dma_bus_interconnect = wishbone.InterconnectShared(
self.dma_bus_interconnect = wishbone.InterconnectShared(
masters = list(self.dma_bus.masters.values()),
slaves = [(self.dma_bus.regions[n].decoder(self.dma_bus), s) for n, s in self.dma_bus.slaves.items()],
register = True)
@ -1191,7 +1191,7 @@ class SoC(LiteXModule):
self.add_config("CPU_HAS_DMA_BUS")
# SoC CSR Interconnect ---------------------------------------------------------------------
self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
self.csr_bankarray = csr_bus.CSRBankArray(self,
address_map = self.csr.address_map,
data_width = self.csr.data_width,
address_width = self.csr.address_width,
@ -1200,7 +1200,7 @@ class SoC(LiteXModule):
ordering = self.csr.ordering,
soc_bus_data_width = self.bus.data_width)
if len(self.csr.masters):
self.submodules.csr_interconnect = csr_bus.InterconnectShared(
self.csr_interconnect = csr_bus.InterconnectShared(
masters = list(self.csr.masters.values()),
slaves = self.csr_bankarray.get_buses())
@ -1298,7 +1298,7 @@ class LiteXSoC(SoC):
identifier += " " + build_time()
else:
self.add_config("BIOS_NO_BUILD_TIME")
setattr(self.submodules, name, Identifier(identifier))
setattr(self, name, Identifier(identifier))
# Add UART -------------------------------------------------------------------------------------
def add_uart(self, name="uart", uart_name="serial", baudrate=115200, fifo_depth=16):
@ -1346,7 +1346,7 @@ class LiteXSoC(SoC):
elif uart_name in ["jtag_uart"]:
from litex.soc.cores.jtag import JTAGPHY
# Run JTAG-UART in sys_jtag clk domain similar to sys clk domain but without sys_rst.
self.clock_domains.cd_sys_jtag = ClockDomain()
self.cd_sys_jtag = ClockDomain()
self.comb += self.cd_sys_jtag.clk.eq(ClockSignal("sys"))
uart_phy = JTAGPHY(device=self.platform.device, clock_domain="sys_jtag", platform=self.platform)
uart = UART(uart_phy, **uart_kwargs)
@ -1373,7 +1373,7 @@ class LiteXSoC(SoC):
usb_pads = self.platform.request("usb")
usb_iobuf = usbio.IoBuf(usb_pads.d_p, usb_pads.d_n, usb_pads.pullup)
# Run USB-ACM in sys_usb clock domain similar to sys_clk domain but without sys_rst.
self.clock_domains.cd_sys_usb = ClockDomain()
self.cd_sys_usb = ClockDomain()
self.comb += self.cd_sys_usb.clk.eq(ClockSignal("sys"))
uart = ClockDomainsRenamer("sys_usb")(cdc_eptri.CDCUsb(usb_iobuf))
@ -1385,9 +1385,9 @@ class LiteXSoC(SoC):
# Add PHY/UART.
if uart_phy is not None:
setattr(self.submodules, name + "_phy", uart_phy)
setattr(self, name + "_phy", uart_phy)
if uart is not None:
setattr(self.submodules, name, uart)
setattr(self, name, uart)
# IRQ.
if self.irq.enabled:
@ -1404,8 +1404,8 @@ class LiteXSoC(SoC):
if clk_freq is None:
clk_freq = self.sys_clk_freq
self.check_if_exists("uartbone")
self.submodules.uartbone_phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
self.submodules.uartbone = uart.UARTBone(phy=self.uartbone_phy, clk_freq=clk_freq, cd=cd)
self.uartbone_phy = uart.UARTPHY(self.platform.request(name), clk_freq, baudrate)
self.uartbone = uart.UARTBone(phy=self.uartbone_phy, clk_freq=clk_freq, cd=cd)
self.bus.add_master(name="uartbone", master=self.uartbone.wishbone)
# Add JTAGbone ---------------------------------------------------------------------------------
@ -1418,8 +1418,8 @@ class LiteXSoC(SoC):
self.check_if_exists(name)
jtagbone_phy = JTAGPHY(device=self.platform.device, chain=chain, platform=self.platform)
jtagbone = uart.UARTBone(phy=jtagbone_phy, clk_freq=self.sys_clk_freq)
setattr(self.submodules, f"{name}_phy", jtagbone_phy)
setattr(self.submodules, name, jtagbone)
setattr(self, f"{name}_phy", jtagbone_phy)
setattr(self, name, jtagbone)
self.bus.add_master(name=name, master=jtagbone.wishbone)
# Add SDRAM ------------------------------------------------------------------------------------
@ -1447,7 +1447,7 @@ class LiteXSoC(SoC):
timing_settings = module.timing_settings,
clk_freq = self.sys_clk_freq,
**kwargs)
setattr(self.submodules, name, sdram)
setattr(self, name, sdram)
# Save SPD data to be able to verify it at runtime.
if hasattr(module, "_spd_data"):
@ -1473,8 +1473,8 @@ class LiteXSoC(SoC):
if with_bist:
sdram_generator = LiteDRAMBISTGenerator(sdram.crossbar.get_port())
sdram_checker = LiteDRAMBISTChecker( sdram.crossbar.get_port())
setattr(self.submodules, f"{name}_generator", sdram_generator)
setattr(self.submodules, f"{name}_checker", sdram_checker)
setattr(self, f"{name}_generator", sdram_generator)
setattr(self, f"{name}_checker", sdram_checker)
if not with_soc_interconnect: return
@ -1589,7 +1589,7 @@ class LiteXSoC(SoC):
reverse = l2_cache_reverse)
if l2_cache_full_memory_we:
l2_cache = FullMemoryWE()(l2_cache)
self.submodules.l2_cache = l2_cache
self.l2_cache = l2_cache
litedram_wb = self.l2_cache.slave
self.add_config("L2_SIZE", l2_cache_size)
else:
@ -1597,7 +1597,7 @@ class LiteXSoC(SoC):
self.submodules += wishbone.Converter(wb_sdram, litedram_wb)
# Wishbone Slave <--> LiteDRAM bridge.
self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(
self.wishbone_bridge = LiteDRAMWishbone2Native(
wishbone = litedram_wb,
port = port,
base_address = self.bus.regions["main_ram"].origin
@ -1635,7 +1635,7 @@ class LiteXSoC(SoC):
ethmac = ClockDomainsRenamer({
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx"})(ethmac)
setattr(self.submodules, name, ethmac)
setattr(self, name, ethmac)
# Compute Regions size and add it to the SoC.
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get(name, None), size=ethmac_region_size, cached=False)
@ -1694,20 +1694,20 @@ class LiteXSoC(SoC):
"eth_tx": phy_cd + "_tx",
"eth_rx": phy_cd + "_rx",
"sys": phy_cd + "_rx"})(ethcore)
setattr(self.submodules, "ethcore_" + name, ethcore)
setattr(self, "ethcore_" + name, ethcore)
etherbone_cd = "sys"
if not with_sys_datapath:
# Create Etherbone clock domain and run it from sys clock domain.
etherbone_cd = name
setattr(self.clock_domains, f"cd_{name}", ClockDomain(name))
setattr(self, f"cd_{name}", ClockDomain(name))
self.comb += getattr(self, f"cd_{name}").clk.eq(ClockSignal("sys"))
self.comb += getattr(self, f"cd_{name}").rst.eq(ResetSignal("sys"))
# Etherbone
self.check_if_exists(name)
etherbone = LiteEthEtherbone(ethcore.udp, udp_port, buffer_depth=buffer_depth, cd=etherbone_cd)
setattr(self.submodules, name, etherbone)
setattr(self, name, etherbone)
self.bus.add_master(master=etherbone.wishbone.bus)
# Timing constraints
@ -1736,12 +1736,12 @@ class LiteXSoC(SoC):
self.check_if_exists(name + "_phy")
spiflash_pads = self.platform.request(name if mode == "1x" else name + mode)
spiflash_phy = LiteSPIPHY(spiflash_pads, module, device=self.platform.device, default_divisor=int(self.sys_clk_freq/clk_freq), rate=rate)
setattr(self.submodules, name + "_phy", spiflash_phy)
setattr(self, name + "_phy", spiflash_phy)
# Core.
self.check_if_exists(name + "_mmap")
spiflash_core = LiteSPI(spiflash_phy, mmap_endianness=self.cpu.endianness, **kwargs)
setattr(self.submodules, name + "_core", spiflash_core)
setattr(self, name + "_core", spiflash_core)
spiflash_region = SoCRegion(origin=self.mem_map.get(name, None), size=module.total_size)
self.bus.add_slave(name=name, slave=spiflash_core.bus, region=spiflash_region)
@ -1786,7 +1786,7 @@ class LiteXSoC(SoC):
spi_clk_freq = spi_clk_freq,
)
spisdcard.add_clk_divider()
setattr(self.submodules, name, spisdcard)
setattr(self, name, spisdcard)
# Debug.
if software_debug:
@ -1814,13 +1814,13 @@ class LiteXSoC(SoC):
# Core.
self.check_if_exists("sdphy")
self.check_if_exists("sdcore")
self.submodules.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
self.submodules.sdcore = SDCore(self.sdphy)
self.sdphy = SDPHY(sdcard_pads, self.platform.device, self.clk_freq, cmd_timeout=10e-1, data_timeout=10e-1)
self.sdcore = SDCore(self.sdphy)
# Block2Mem DMA.
if "read" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
self.submodules.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.sdblock2mem = SDBlock2MemDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdcore.source.connect(self.sdblock2mem.sink)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sdblock2mem", master=bus)
@ -1828,13 +1828,13 @@ class LiteXSoC(SoC):
# Mem2Block DMA.
if "write" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
self.submodules.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
self.sdmem2block = SDMem2BlockDMA(bus=bus, endianness=self.cpu.endianness)
self.comb += self.sdmem2block.source.connect(self.sdcore.sink)
dma_bus = self.bus if not hasattr(self, "dma_bus") else self.dma_bus
dma_bus.add_master("sdmem2block", master=bus)
# Interrupts.
self.submodules.sdirq = EventManager()
self.sdirq = EventManager()
self.sdirq.card_detect = EventSourcePulse(description="SDCard has been ejected/inserted.")
if "read" in mode:
self.sdirq.block2mem_dma = EventSourcePulse(description="Block2Mem DMA terminated.")
@ -1877,22 +1877,21 @@ class LiteXSoC(SoC):
# Core.
self.check_if_exists("sata_core")
self.submodules.sata_core = LiteSATACore(phy)
self.sata_core = LiteSATACore(phy)
# Crossbar.
self.check_if_exists("sata_crossbar")
self.submodules.sata_crossbar = LiteSATACrossbar(self.sata_core)
self.sata_crossbar = LiteSATACrossbar(self.sata_core)
# Identify.
if with_identify:
sata_identify = LiteSATAIdentify(self.sata_crossbar.get_port())
self.submodules += sata_identify
self.submodules.sata_identify = LiteSATAIdentifyCSR(sata_identify)
self.sata_identify = LiteSATAIdentifyCSR(sata_identify)
# Sector2Mem DMA.
if "read" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
self.submodules.sata_sector2mem = LiteSATASector2MemDMA(
self.sata_sector2mem = LiteSATASector2MemDMA(
port = self.sata_crossbar.get_port(),
bus = bus,
endianness = self.cpu.endianness)
@ -1902,7 +1901,7 @@ class LiteXSoC(SoC):
# Mem2Sector DMA.
if "write" in mode:
bus = wishbone.Interface(data_width=self.bus.data_width, adr_width=self.bus.get_address_width(standard="wishbone"))
self.submodules.sata_mem2sector = LiteSATAMem2SectorDMA(
self.sata_mem2sector = LiteSATAMem2SectorDMA(
bus = bus,
port = self.sata_crossbar.get_port(),
endianness = self.cpu.endianness)
@ -1910,7 +1909,7 @@ class LiteXSoC(SoC):
dma_bus.add_master("sata_mem2sector", master=bus)
# Interrupts.
self.submodules.sata_irq = EventManager()
self.sata_irq = EventManager()
if "read" in mode:
self.sata_irq.sector2mem_dma = EventSourcePulse(description="Sector2Mem DMA terminated.")
if "write" in mode:
@ -1952,19 +1951,19 @@ class LiteXSoC(SoC):
endianness = phy.endianness,
address_width = address_width
)
setattr(self.submodules, f"{name}_endpoint", endpoint)
setattr(self, f"{name}_endpoint", endpoint)
# MMAP.
self.check_if_exists(f"{name}_mmap")
mmap = LitePCIeWishboneMaster(self.pcie_endpoint, base_address=self.mem_map["csr"])
setattr(self.submodules, f"{name}_mmap", mmap)
setattr(self, f"{name}_mmap", mmap)
self.bus.add_master(master=mmap.wishbone)
# MSI.
if with_msi:
self.check_if_exists(f"{name}_msi")
msi = LitePCIeMSI()
setattr(self.submodules, f"{name}_msi", msi)
setattr(self, f"{name}_msi", msi)
self.comb += msi.source.connect(phy.msi)
self.msis = {}
@ -1978,7 +1977,7 @@ class LiteXSoC(SoC):
with_synchronizer = with_synchronizer,
address_width = address_width
)
setattr(self.submodules, f"{name}_dma{i}", dma)
setattr(self, f"{name}_dma{i}", dma)
self.msis[f"{name.upper()}_DMA{i}_WRITER"] = dma.writer.irq
self.msis[f"{name.upper()}_DMA{i}_READER"] = dma.reader.irq
self.add_constant("DMA_CHANNELS", ndmas)
@ -2002,12 +2001,12 @@ class LiteXSoC(SoC):
self.check_if_exists(f"{name}_vtg")
vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
vtg = ClockDomainsRenamer(clock_domain)(vtg)
setattr(self.submodules, f"{name}_vtg", vtg)
setattr(self, f"{name}_vtg", vtg)
# ColorsBars Pattern.
self.check_if_exists(name)
colorbars = ClockDomainsRenamer(clock_domain)(ColorBarsPattern())
setattr(self.submodules, name, colorbars)
setattr(self, name, colorbars)
# Connect Video Timing Generator to ColorsBars Pattern.
self.comb += [
@ -2024,7 +2023,7 @@ class LiteXSoC(SoC):
self.check_if_exists(f"{name}_vtg")
vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
vtg = ClockDomainsRenamer(clock_domain)(vtg)
setattr(self.submodules, f"{name}_vtg", vtg)
setattr(self, f"{name}_vtg", vtg)
# Video Terminal.
timings = timings if isinstance(timings, str) else timings[0]
@ -2033,14 +2032,14 @@ class LiteXSoC(SoC):
vres = int(timings.split("@")[0].split("x")[1]),
)
vt = ClockDomainsRenamer(clock_domain)(vt)
setattr(self.submodules, name, vt)
setattr(self, name, vt)
# Connect Video Timing Generator to Video Terminal.
self.comb += vtg.source.connect(vt.vtg_sink)
# Connect UART to Video Terminal.
uart_cdc = stream.ClockDomainCrossing([("data", 8)], cd_from="sys", cd_to=clock_domain)
setattr(self.submodules, f"{name}_uart_cdc", uart_cdc)
setattr(self, f"{name}_uart_cdc", uart_cdc)
self.comb += [
uart_cdc.sink.valid.eq(self.uart.tx_fifo.source.valid & self.uart.tx_fifo.source.ready),
uart_cdc.sink.data.eq(self.uart.tx_fifo.source.data),
@ -2058,7 +2057,7 @@ class LiteXSoC(SoC):
# Video Timing Generator.
vtg = VideoTimingGenerator(default_video_timings=timings if isinstance(timings, str) else timings[1])
vtg = ClockDomainsRenamer(clock_domain)(vtg)
setattr(self.submodules, f"{name}_vtg", vtg)
setattr(self, f"{name}_vtg", vtg)
# Video FrameBuffer.
timings = timings if isinstance(timings, str) else timings[0]
@ -2073,7 +2072,7 @@ class LiteXSoC(SoC):
clock_domain = clock_domain,
clock_faster_than_sys = vtg.video_timings["pix_clk"] >= self.sys_clk_freq,
)
setattr(self.submodules, name, vfb)
setattr(self, name, vfb)
# Connect Video Timing Generator to Video FrameBuffer.
self.comb += vtg.source.connect(vfb.vtg_sink)