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soc/cores/spi: make sure done and miso are synchronous.

This commit is contained in:
Florent Kermarrec 2020-07-17 15:38:52 +02:00
parent 754f140a9d
commit 1f34f6ef00
1 changed files with 4 additions and 2 deletions
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6
litex/soc/cores/spi.py
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@ -41,6 +41,7 @@ class SPIMaster(Module, AutoCSR):
# # # # # #
done = Signal()
bits = Signal(8) bits = Signal(8)
xfer = Signal() xfer = Signal()
shift = Signal() shift = Signal()
@ -64,7 +65,7 @@ class SPIMaster(Module, AutoCSR):
# Control FSM ------------------------------------------------------------------------------ # Control FSM ------------------------------------------------------------------------------
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
self.done.eq(1), done.eq(1),
If(self.start, If(self.start,
NextValue(bits, 0), NextValue(bits, 0),
NextState("WAIT-CLK-FALL") NextState("WAIT-CLK-FALL")
@ -91,6 +92,7 @@ class SPIMaster(Module, AutoCSR):
shift.eq(1), shift.eq(1),
self.irq.eq(1) self.irq.eq(1)
) )
self.sync += self.done.eq(done & ~self.start)
# Chip Select generation ------------------------------------------------------------------- # Chip Select generation -------------------------------------------------------------------
if hasattr(pads, "cs_n"): if hasattr(pads, "cs_n"):
@ -125,7 +127,7 @@ class SPIMaster(Module, AutoCSR):
If(clk_fall & shift, If(clk_fall & shift,
miso_data.eq(Cat(miso, miso_data)) miso_data.eq(Cat(miso, miso_data))
), ),
If(self.done, self.miso.eq(miso_data)), If(done, self.miso.eq(miso_data)),
] ]
def add_csr(self, with_cs=True, with_loopback=True): def add_csr(self, with_cs=True, with_loopback=True):