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soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.

This commit is contained in:
Florent Kermarrec 2024-08-20 10:40:24 +02:00
parent a960dc33bc
commit 1f71f3d68b
1 changed files with 11 additions and 5 deletions
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16
litex/soc/cores/hyperbus.py
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@ -91,16 +91,22 @@ class HyperRAM(LiteXModule):
self.comb += pads.rst_n.eq(1 & ~self.conf_rst) self.comb += pads.rst_n.eq(1 & ~self.conf_rst)
# CSn. # CSn.
self.comb += pads.cs_n[0].eq(~cs) self.comb += [
assert len(pads.cs_n) <= 2 # Set reset value.
if len(pads.cs_n) == 2: pads.cs_n.eq(2**len(pads.cs_n)),
self.comb += pads.cs_n[1].eq(1) # Set CSn.
pads.cs_n[0].eq(~cs)
]
# Clk. # Clk.
if hasattr(pads, "clk"): if hasattr(pads, "clk"):
# Single Ended Clk.
self.comb += pads.clk.eq(clk) self.comb += pads.clk.eq(clk)
else: elif hastattr(pads, "clk_p"):
# Differential Clk.
self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n) self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n)
else:
raise ValueError
# Burst Timer ------------------------------------------------------------------------------ # Burst Timer ------------------------------------------------------------------------------
if sys_clk_freq is None: if sys_clk_freq is None: