soc/cores/hyperbus: Cleanup CSn/Clk generation and add comments.
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@ -91,16 +91,22 @@ class HyperRAM(LiteXModule):
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self.comb += pads.rst_n.eq(1 & ~self.conf_rst)
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# CSn.
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self.comb += pads.cs_n[0].eq(~cs)
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assert len(pads.cs_n) <= 2
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if len(pads.cs_n) == 2:
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self.comb += pads.cs_n[1].eq(1)
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self.comb += [
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# Set reset value.
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pads.cs_n.eq(2**len(pads.cs_n)),
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# Set CSn.
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pads.cs_n[0].eq(~cs)
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]
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# Clk.
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if hasattr(pads, "clk"):
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# Single Ended Clk.
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self.comb += pads.clk.eq(clk)
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else:
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elif hastattr(pads, "clk_p"):
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# Differential Clk.
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self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n)
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else:
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raise ValueError
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# Burst Timer ------------------------------------------------------------------------------
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if sys_clk_freq is None:
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