soc: add LiteXSoC class and mode add_identifier/uart/sdram to it
This commit is contained in:
Florent Kermarrec
parent
11dbe19084
commit
1faefdc0fa
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@ -759,7 +759,98 @@ class SoC(Module):
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self.add_config("CPU_VARIANT", str(variant.split('+')[0]))
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self.add_config("CPU_RESET_ADDR", reset_address)
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# SoC Main Peripherals -------------------------------------------------------------------------
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def add_timer(self, name="timer0"):
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self.check_if_exists(name)
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setattr(self.submodules, name, Timer())
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self.csr.add(name, use_loc_if_exists=True)
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self.irq.add(name, use_loc_if_exists=True)
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# SoC finalization -----------------------------------------------------------------------------
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def do_finalize(self):
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self.logger.info(colorer("-"*80, color="bright"))
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self.logger.info(colorer("Finalized SoC:"))
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self.logger.info(colorer("-"*80, color="bright"))
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self.logger.info(self.bus)
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self.logger.info(self.csr)
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self.logger.info(self.irq)
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self.logger.info(colorer("-"*80, color="bright"))
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# SoC Bus Interconnect ---------------------------------------------------------------------
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bus_masters = self.bus.masters.values()
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bus_slaves = [(self.bus.regions[n].decoder(), s) for n, s in self.bus.slaves.items()]
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if len(bus_masters) and len(bus_slaves):
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self.submodules.bus_interconnect = wishbone.InterconnectShared(
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masters = bus_masters,
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slaves = bus_slaves,
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register = True,
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timeout_cycles = self.bus.timeout)
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if hasattr(self, "ctrl") and self.bus.timeout is not None:
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self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
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# SoC CSR Interconnect ---------------------------------------------------------------------
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self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
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address_map = self.csr.address_map,
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data_width = self.csr.data_width,
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address_width = self.csr.address_width,
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alignment = self.csr.alignment
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)
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if len(self.csr.masters):
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self.submodules.csr_interconnect = csr_bus.InterconnectShared(
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masters = list(self.csr.masters.values()),
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slaves = self.csr_bankarray.get_buses())
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# Add CSRs regions
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for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
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self.csr.add_region(name, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busword = self.csr.data_width,
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obj = csrs))
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# Add Memory regions
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for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
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self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busworkd = self.csr.data_width,
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obj = memory))
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# Sort CSR regions by origin
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self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
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# Add CSRs / Config items to constants
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for name, constant in self.csr_bankarray.constants:
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self.add_constant(name + "_" + constant.name, constant.value.value)
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# SoC CPU Check ----------------------------------------------------------------------------
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if not isinstance(self.cpu, cpu.CPUNone):
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for name in ["rom", "sram"]:
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if name not in list(self.bus.regions.keys()) + list(self.bus.ld_regions.keys()):
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self.logger.error("CPU needs {} Region to be defined as Bus or Linker Region.".format(
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colorer(name, color="red")))
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self.logger.error(self.bus)
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raise
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# SoC IRQ Interconnect ---------------------------------------------------------------------
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if hasattr(self, "cpu"):
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if hasattr(self.cpu, "interrupt"):
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for name, loc in sorted(self.irq.locs.items()):
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if name in self.cpu.interrupts.keys():
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continue
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if hasattr(self, name):
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module = getattr(self, name)
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if not hasattr(module, "ev"):
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self.logger.error("No EventManager found on {} SubModule".format(
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colorer(name, color="red")))
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self.comb += self.cpu.interrupt[loc].eq(module.ev.irq)
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self.add_constant(name + "_INTERRUPT", loc)
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# SoC build ------------------------------------------------------------------------------------
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def build(self, *args, **kwargs):
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return self.platform.build(self, *args, **kwargs)
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# LiteXSoC -----------------------------------------------------------------------------------------
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class LiteXSoC(SoC):
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# Add Identifier -------------------------------------------------------------------------------
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def add_identifier(self, name="identifier", identifier="LiteX SoC", with_build_time=True):
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self.check_if_exists(name)
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if with_build_time:
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@ -767,12 +858,7 @@ class SoC(Module):
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setattr(self.submodules, name, Identifier(ident))
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self.csr.add(name + "_mem", use_loc_if_exists=True)
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def add_timer(self, name="timer0"):
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self.check_if_exists(name)
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setattr(self.submodules, name, Timer())
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self.csr.add(name, use_loc_if_exists=True)
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self.irq.add(name, use_loc_if_exists=True)
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# Add UART -------------------------------------------------------------------------------------
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def add_uart(self, name, baudrate=115200):
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from litex.soc.cores import uart
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if name in ["stub", "stream"]:
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@ -804,6 +890,7 @@ class SoC(Module):
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self.csr.add("uart", use_loc_if_exists=True)
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self.irq.add("uart", use_loc_if_exists=True)
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# Add SDRAM ------------------------------------------------------------------------------------
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def add_sdram(self, name,
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phy,
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geom_settings,
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@ -895,85 +982,3 @@ class SoC(Module):
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# L2 Cache <--> LiteDRAM bridge --------------------------------------------------------
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self.submodules.wishbone_bridge = LiteDRAMWishbone2Native(self.l2_cache.slave, port)
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# SoC finalization -----------------------------------------------------------------------------
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def do_finalize(self):
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self.logger.info(colorer("-"*80, color="bright"))
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self.logger.info(colorer("Finalized SoC:"))
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self.logger.info(colorer("-"*80, color="bright"))
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self.logger.info(self.bus)
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self.logger.info(self.csr)
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self.logger.info(self.irq)
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self.logger.info(colorer("-"*80, color="bright"))
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# SoC Bus Interconnect ---------------------------------------------------------------------
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bus_masters = self.bus.masters.values()
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bus_slaves = [(self.bus.regions[n].decoder(), s) for n, s in self.bus.slaves.items()]
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if len(bus_masters) and len(bus_slaves):
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self.submodules.bus_interconnect = wishbone.InterconnectShared(
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masters = bus_masters,
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slaves = bus_slaves,
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register = True,
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timeout_cycles = self.bus.timeout)
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if hasattr(self, "ctrl") and self.bus.timeout is not None:
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self.comb += self.ctrl.bus_error.eq(self.bus_interconnect.timeout.error)
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# SoC CSR Interconnect ---------------------------------------------------------------------
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self.submodules.csr_bankarray = csr_bus.CSRBankArray(self,
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address_map = self.csr.address_map,
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data_width = self.csr.data_width,
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address_width = self.csr.address_width,
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alignment = self.csr.alignment
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)
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if len(self.csr.masters):
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self.submodules.csr_interconnect = csr_bus.InterconnectShared(
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masters = list(self.csr.masters.values()),
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slaves = self.csr_bankarray.get_buses())
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# Add CSRs regions
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for name, csrs, mapaddr, rmap in self.csr_bankarray.banks:
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self.csr.add_region(name, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busword = self.csr.data_width,
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obj = csrs))
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# Add Memory regions
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for name, memory, mapaddr, mmap in self.csr_bankarray.srams:
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self.csr.add_region(name + "_" + memory.name_override, SoCCSRRegion(
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origin = (self.bus.regions["csr"].origin + self.csr.paging*mapaddr),
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busworkd = self.csr.data_width,
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obj = memory))
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# Sort CSR regions by origin
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self.csr.regions = {k: v for k, v in sorted(self.csr.regions.items(), key=lambda item: item[1].origin)}
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# Add CSRs / Config items to constants
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for name, constant in self.csr_bankarray.constants:
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self.add_constant(name + "_" + constant.name, constant.value.value)
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# SoC CPU Check ----------------------------------------------------------------------------
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if not isinstance(self.cpu, cpu.CPUNone):
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for name in ["rom", "sram"]:
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if name not in list(self.bus.regions.keys()) + list(self.bus.ld_regions.keys()):
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self.logger.error("CPU needs {} Region to be defined as Bus or Linker Region.".format(
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colorer(name, color="red")))
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self.logger.error(self.bus)
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raise
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# SoC IRQ Interconnect ---------------------------------------------------------------------
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if hasattr(self, "cpu"):
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if hasattr(self.cpu, "interrupt"):
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for name, loc in sorted(self.irq.locs.items()):
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if name in self.cpu.interrupts.keys():
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continue
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if hasattr(self, name):
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module = getattr(self, name)
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if not hasattr(module, "ev"):
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self.logger.error("No EventManager found on {} SubModule".format(
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colorer(name, color="red")))
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self.comb += self.cpu.interrupt[loc].eq(module.ev.irq)
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self.add_constant(name + "_INTERRUPT", loc)
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# SoC build ------------------------------------------------------------------------------------
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def build(self, *args, **kwargs):
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return self.platform.build(self, *args, **kwargs)
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@ -39,7 +39,7 @@ __all__ = [
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# SoCCore ------------------------------------------------------------------------------------------
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class SoCCore(SoC):
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class SoCCore(LiteXSoC):
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# default register/interrupt/memory mappings (can be redefined by user)
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csr_map = {}
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interrupt_map = {}
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@ -85,8 +85,8 @@ class SoCCore(SoC):
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# Others
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**kwargs):
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# New SoC class ----------------------------------------------------------------------------
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SoC.__init__(self, platform, clk_freq,
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# New LiteXSoC class ----------------------------------------------------------------------------
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LiteXSoC.__init__(self, platform, clk_freq,
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bus_standard = "wishbone",
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bus_data_width = 32,
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bus_address_width = 32,
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