soc/integration/soc_core: add csr_map_update function
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@ -10,7 +10,14 @@ from litex.soc.interconnect.csr import *
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from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
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from litex.soc.interconnect import wishbone, csr_bus, wishbone2csr
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__all__ = ["mem_decoder", "get_mem_data", "SoCCore", "soc_core_args", "soc_core_argdict"]
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__all__ = [
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"mem_decoder",
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"get_mem_data",
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"csr_map_update",
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"SoCCore",
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"soc_core_args",
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"soc_core_argdict"
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]
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def version(with_time=True):
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def version(with_time=True):
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@ -61,6 +68,11 @@ class ReadOnlyDict(dict):
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del __readonly__
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del __readonly__
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def csr_map_update(csr_map, csr_peripherals):
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csr_map.update(dict((n, v)
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for v, n in enumerate(csr_peripherals, start=max(csr_map.values()) + 1)))
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class SoCController(Module, AutoCSR):
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class SoCController(Module, AutoCSR):
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def __init__(self):
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def __init__(self):
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self._reset = CSR()
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self._reset = CSR()
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