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uart: generate ack for rx (serialboot OK with sim)

This commit is contained in:
Florent Kermarrec 2015-03-04 00:57:37 +01:00
parent 7c058a52c9
commit 200791c81d
2 changed files with 4 additions and 2 deletions
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3
misoclib/com/uart/__init__.py
View File

@ -26,5 +26,6 @@ class UART(Module, AutoCSR):
] ]
self.comb += [ self.comb += [
self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack), self.ev.tx.trigger.eq(phy.sink.stb & phy.sink.ack),
self.ev.rx.trigger.eq(phy.source.stb) #phy.source.ack supposed to be always 1 self.ev.rx.trigger.eq(phy.source.stb & phy.source.ack),
phy.source.ack.eq(~self.ev.rx.pending)
] ]

3
misoclib/com/uart/phy/sim.py
View File

@ -12,5 +12,6 @@ class UARTPHYSim(Module):
self.sink.ack.eq(pads.source_ack), self.sink.ack.eq(pads.source_ack),
self.source.stb.eq(pads.sink_stb), self.source.stb.eq(pads.sink_stb),
self.source.data.eq(pads.sink_data) self.source.data.eq(pads.sink_data),
pads.sink_ack.eq(self.source.ack)
] ]