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targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)

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This commit is contained in:
Florent Kermarrec 2019-12-03 09:05:52 +01:00
parent 6b82064723
commit 201d60f37a
1 changed files with 2 additions and 2 deletions
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4
litex/boards/targets/netv2.py
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@ -13,7 +13,7 @@ from litex.soc.cores.clock import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *
from litedram.modules import MT41J128M16
from litedram.modules import K4B2G1646F
from litedram.phy import s7ddrphy
from liteeth.phy.rmii import LiteEthPHYRMII
@ -69,7 +69,7 @@ class BaseSoC(SoCSDRAM):
nphases = 4,
sys_clk_freq = sys_clk_freq)
self.add_csr("ddrphy")
sdram_module = MT41J128M16(sys_clk_freq, "1:4")
sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
self.register_sdram(self.ddrphy,
geom_settings = sdram_module.geom_settings,
timing_settings = sdram_module.timing_settings)