targets/netv2: switch to MVP DDR3 (K4B2G1646F instead of MT41J128M16)
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@ -13,7 +13,7 @@ from litex.soc.cores.clock import *
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from litex.soc.integration.soc_sdram import *
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from litex.soc.integration.builder import *
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from litedram.modules import MT41J128M16
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from litedram.modules import K4B2G1646F
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from litedram.phy import s7ddrphy
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from liteeth.phy.rmii import LiteEthPHYRMII
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@ -69,7 +69,7 @@ class BaseSoC(SoCSDRAM):
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nphases = 4,
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sys_clk_freq = sys_clk_freq)
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self.add_csr("ddrphy")
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sdram_module = MT41J128M16(sys_clk_freq, "1:4")
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sdram_module = K4B2G1646F(sys_clk_freq, "1:4")
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self.register_sdram(self.ddrphy,
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geom_settings = sdram_module.geom_settings,
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timing_settings = sdram_module.timing_settings)
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