integration/soc/add_etherbone: Allow 64-bit support now that validated.

2024-09-12 13:38:13 +02:00 · 2024-09-12 13:38:13 +02:00 · 203c9816b2
parent b41a526e81
commit 203c9816b2
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc.py
+++ b/litex/soc/integration/soc.py
@ -1956,7 +1956,7 @@ class LiteXSoC(SoC):
        from liteeth.phy.model import LiteEthPHYModel

        # Core
-        assert data_width in [8, 32]
+        assert data_width in [8, 32, 64]
        with_sys_datapath = (data_width == 32)
        self.check_if_exists(name + "_ethcore")
        ethcore = LiteEthUDPIPCore(