Hardware
/
litex
mirror of https://github.com/enjoy-digital/litex.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

integration/soc/add_etherbone: Allow 64-bit support now that validated.

This commit is contained in:
Florent Kermarrec 2024-09-12 13:38:13 +02:00
parent b41a526e81
commit 203c9816b2
1 changed files with 1 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
litex/soc/integration/soc.py
View File

@ -1956,7 +1956,7 @@ class LiteXSoC(SoC):
from liteeth.phy.model import LiteEthPHYModel from liteeth.phy.model import LiteEthPHYModel
# Core # Core
assert data_width in [8, 32] assert data_width in [8, 32, 64]
with_sys_datapath = (data_width == 32) with_sys_datapath = (data_width == 32)
self.check_if_exists(name + "_ethcore") self.check_if_exists(name + "_ethcore")
ethcore = LiteEthUDPIPCore( ethcore = LiteEthUDPIPCore(