Wishbone: omit fixed LSBs
This commit is contained in:
parent
077fd9fdbc
commit
20425703fa
|
@ -4,7 +4,7 @@ from migen.corelogic.misc import multimux, optree
|
|||
from migen.bus.simple import Simple, get_sig_name
|
||||
|
||||
_desc = [
|
||||
(True, "adr", 32),
|
||||
(True, "adr", 30),
|
||||
(True, "dat", 32),
|
||||
(False, "dat", 32),
|
||||
(True, "sel", 4),
|
||||
|
|
|
@ -16,7 +16,7 @@ class Inst():
|
|||
sync = [
|
||||
self.csr.we_o.eq(0),
|
||||
self.csr.d_o.eq(self.wishbone.dat_i),
|
||||
self.csr.a_o.eq(self.wishbone.adr_i[2:16]),
|
||||
self.csr.a_o.eq(self.wishbone.adr_i[:14]),
|
||||
self.wishbone.dat_o.eq(self.csr.d_i)
|
||||
]
|
||||
return Fragment(sync=sync) + self.timeline.get_fragment()
|
||||
|
|
Loading…
Reference in New Issue