framebuffer/dvi: TMDS encoder test bench
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@ -9,7 +9,7 @@ class Encoder(Module):
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self.c = Signal(2)
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self.de = Signal()
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self.output = Signal(10)
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self.out = Signal(10)
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###
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@ -44,7 +44,7 @@ class Encoder(Module):
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]
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# stage 4 - final encoding
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cnt = Signal((5, True))
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cnt = Signal((6, True))
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s_c = self.c
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s_de = self.de
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@ -56,33 +56,91 @@ class Encoder(Module):
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self.sync += If(s_de,
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If((cnt == 0) | (n1q_m == n0q_m),
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self.output[9].eq(~q_m_r[8]),
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self.output[8].eq(q_m_r[8]),
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self.out[9].eq(~q_m_r[8]),
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self.out[8].eq(q_m_r[8]),
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If(q_m_r[8],
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self.output[:8].eq(q_m_r[:8]),
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self.out[:8].eq(q_m_r[:8]),
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cnt.eq(cnt + n1q_m - n0q_m)
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).Else(
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self.output[:8].eq(~q_m_r[:8]),
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self.out[:8].eq(~q_m_r[:8]),
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cnt.eq(cnt + n0q_m - n1q_m)
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)
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).Else(
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If((~cnt[4] & (n1q_m > n0q_m)) | (cnt[4] & (n0q_m > n1q_m)),
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self.output[9].eq(1),
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self.output[8].eq(q_m_r[8]),
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self.output[:8].eq(~q_m_r[:8]),
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If((~cnt[5] & (n1q_m > n0q_m)) | (cnt[5] & (n0q_m > n1q_m)),
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self.out[9].eq(1),
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self.out[8].eq(q_m_r[8]),
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self.out[:8].eq(~q_m_r[:8]),
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cnt.eq(cnt + Cat(0, q_m_r[8]) + n0q_m - n1q_m)
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).Else(
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self.output[9].eq(0),
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self.output[8].eq(q_m_r[8]),
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self.output[:8].eq(q_m_r[:8]),
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self.out[9].eq(0),
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self.out[8].eq(q_m_r[8]),
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self.out[:8].eq(q_m_r[:8]),
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cnt.eq(cnt - Cat(0, ~q_m_r[8]) + n1q_m - n0q_m)
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)
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)
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).Else(
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self.output.eq(Array(control_tokens)[s_c]),
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self.out.eq(Array(control_tokens)[s_c]),
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cnt.eq(0)
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)
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class _EncoderTB(Module):
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def __init__(self, inputs):
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self.outs = []
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self._iter_inputs = iter(inputs)
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self._end_cycle = None
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self.submodules.dut = Encoder()
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self.comb += self.dut.de.eq(1)
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def do_simulation(self, s):
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if self._end_cycle is None:
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try:
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nv = next(self._iter_inputs)
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except StopIteration:
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self._end_cycle = s.cycle_counter + 4
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else:
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s.wr(self.dut.d, nv)
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if s.cycle_counter == self._end_cycle:
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s.interrupt = True
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if s.cycle_counter > 4:
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self.outs.append(s.rd(self.dut.out))
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def _bit(i, n):
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return (i >> n) & 1
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def _decode_tmds(b):
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try:
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c = control_tokens.index(b)
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de = False
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except ValueError:
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c = 0
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de = True
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vsync = bool(c & 2)
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hsync = bool(c & 1)
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value = _bit(b, 0) ^ _bit(b, 9)
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for i in range(1, 8):
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value |= (_bit(b, i) ^ _bit(b, i-1) ^ (~_bit(b, 8) & 1)) << i
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return de, hsync, vsync, value
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if __name__ == "__main__":
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from migen.fhdl import verilog
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print(verilog.convert(Encoder()))
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from migen.sim.generic import Simulator
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from random import Random
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rng = Random(788)
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test_list = [rng.randrange(256) for i in range(500)]
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tb = _EncoderTB(test_list)
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Simulator(tb).run()
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check = [_decode_tmds(out)[3] for out in tb.outs]
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assert(check == test_list)
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nb0 = 0
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nb1 = 0
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for out in tb.outs:
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for i in range(10):
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if _bit(out, i):
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nb1 += 1
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else:
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nb0 += 1
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print("0/1: {}/{} ({:.2f})".format(nb0, nb1, nb0/nb1))
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