mirror of
https://github.com/enjoy-digital/litex.git
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litepcie: use new Migen modules from actorlib (avoid duplications between cores)
This commit is contained in:
Florent Kermarrec
parent
1ef81c4d24
commit
20dd6d3047
9 changed files with 78 additions and 172 deletions
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@ -1,6 +1,8 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.genlib.misc import reverse_bytes
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from migen.flow.actor import *
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from migen.actorlib.packet import Arbiter, Dispatcher
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KB = 1024
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MB = 1024*KB
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@ -18,15 +20,6 @@ def get_bar_mask(size):
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size = size >> 1
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return mask
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def reverse_bytes(v):
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return Cat(v[24:32], v[16:24], v[8:16], v[0:8])
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def reverse_bits(v):
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return Cat(v[3], v[2], v[1], v[0])
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def phy_layout(dw):
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layout = [
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("dat", dw),
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@ -1,6 +1,7 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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from migen.flow.actor import EndpointDescription, Sink, Source
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from migen.actorlib.packet import HeaderField, Header
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from misoclib.com.litepcie.common import *
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@ -26,92 +27,91 @@ max_request_size = 512
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# headers
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class HField():
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def __init__(self, word, offset, width):
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self.word = word
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self.offset = offset
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self.width = width
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tlp_header_w = 128
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tlp_common_header = {
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"fmt": HField(0, 29, 2),
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"type": HField(0, 24, 5),
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tlp_common_header_length = 16
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tlp_common_header_fields = {
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"fmt": HeaderField(0*4, 29, 2),
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"type": HeaderField(0*4, 24, 5),
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}
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tlp_common_header = Header(tlp_common_header_fields,
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tlp_common_header_length,
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swap_field_bytes=False)
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tlp_request_header = {
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"fmt": HField(0, 29, 2),
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"type": HField(0, 24, 5),
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"tc": HField(0, 20, 3),
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"td": HField(0, 15, 1),
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"ep": HField(0, 14, 1),
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"attr": HField(0, 12, 2),
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"length": HField(0, 0, 10),
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"requester_id": HField(1, 16, 16),
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"tag": HField(1, 8, 8),
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"last_be": HField(1, 4, 4),
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"first_be": HField(1, 0, 4),
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tlp_request_header_length = 16
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tlp_request_header_fields = {
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"fmt": HeaderField(0*4, 29, 2),
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"type": HeaderField(0*4, 24, 5),
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"tc": HeaderField(0*4, 20, 3),
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"td": HeaderField(0*4, 15, 1),
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"ep": HeaderField(0*4, 14, 1),
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"attr": HeaderField(0*4, 12, 2),
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"length": HeaderField(0*4, 0, 10),
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"address": HField(2, 2, 30),
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"requester_id": HeaderField(1*4, 16, 16),
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"tag": HeaderField(1*4, 8, 8),
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"last_be": HeaderField(1*4, 4, 4),
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"first_be": HeaderField(1*4, 0, 4),
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"address": HeaderField(2*4, 2, 30),
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}
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tlp_request_header = Header(tlp_request_header_fields,
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tlp_request_header_length,
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swap_field_bytes=False)
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tlp_completion_header = {
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"fmt": HField(0, 29, 2),
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"type": HField(0, 24, 5),
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"tc": HField(0, 20, 3),
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"td": HField(0, 15, 1),
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"ep": HField(0, 14, 1),
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"attr": HField(0, 12, 2),
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"length": HField(0, 0, 10),
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"completer_id": HField(1, 16, 16),
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"status": HField(1, 13, 3),
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"bcm": HField(1, 12, 1),
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"byte_count": HField(1, 0, 12),
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tlp_completion_header_length = 16
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tlp_completion_header_fields = {
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"fmt": HeaderField(0*4, 29, 2),
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"type": HeaderField(0*4, 24, 5),
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"tc": HeaderField(0*4, 20, 3),
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"td": HeaderField(0*4, 15, 1),
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"ep": HeaderField(0*4, 14, 1),
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"attr": HeaderField(0*4, 12, 2),
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"length": HeaderField(0*4, 0, 10),
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"requester_id": HField(2, 16, 16),
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"tag": HField(2, 8, 8),
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"lower_address": HField(2, 0, 7),
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"completer_id": HeaderField(1*4, 16, 16),
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"status": HeaderField(1*4, 13, 3),
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"bcm": HeaderField(1*4, 12, 1),
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"byte_count": HeaderField(1*4, 0, 12),
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"requester_id": HeaderField(2*4, 16, 16),
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"tag": HeaderField(2*4, 8, 8),
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"lower_address": HeaderField(2*4, 0, 7),
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}
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tlp_completion_header = Header(tlp_completion_header_fields,
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tlp_completion_header_length,
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swap_field_bytes=False)
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# layouts
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def _layout_from_header(header):
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_layout = []
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for k, v in sorted(header.items()):
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_layout.append((k, v.width))
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return _layout
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def tlp_raw_layout(dw):
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layout = [
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("header", tlp_header_w),
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("dat", dw),
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("be", dw//8)
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("header", 4*32),
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("dat", dw),
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("be", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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def tlp_common_layout(dw):
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layout = _layout_from_header(tlp_common_header) + [
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("dat", dw),
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("be", dw//8)
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layout = tlp_common_header.get_layout() + [
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("dat", dw),
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("be", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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def tlp_request_layout(dw):
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layout = _layout_from_header(tlp_request_header) + [
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("dat", dw),
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("be", dw//8)
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layout = tlp_request_header.get_layout() + [
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("dat", dw),
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("be", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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def tlp_completion_layout(dw):
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layout = _layout_from_header(tlp_completion_header) + [
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("dat", dw),
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("be", dw//8)
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layout = tlp_completion_header.get_layout() + [
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("dat", dw),
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("be", dw//8)
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]
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return EndpointDescription(layout, packetized=True)
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@ -3,16 +3,6 @@ from migen.actorlib.structuring import *
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from migen.genlib.fsm import FSM, NextState
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from misoclib.com.litepcie.core.packet.common import *
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from misoclib.com.litepcie.core.switch.dispatcher import Dispatcher
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def _decode_header(h_dict, h_signal, obj):
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r = []
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for k, v in sorted(h_dict.items()):
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start = v.word*32+v.offset
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end = start+v.width
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r.append(getattr(obj, k).eq(h_signal[start:end]))
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return r
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class HeaderExtracter(Module):
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@ -65,7 +55,7 @@ class HeaderExtracter(Module):
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source.sop.eq(sop),
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source.eop.eq(sink.eop),
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source.dat.eq(Cat(reverse_bytes(sink_dat_r[32:]), reverse_bytes(sink.dat[:32]))),
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source.be.eq(Cat(reverse_bits(sink_be_r[4:]), reverse_bits(sink.be[:4]))),
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source.be.eq(Cat(freversed(sink_be_r[4:]), freversed(sink.be[:4]))),
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If(source.stb & source.ack & source.eop,
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NextState("HEADER1")
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)
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@ -82,7 +72,7 @@ class HeaderExtracter(Module):
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source.sop.eq(1),
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source.eop.eq(1),
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source.dat.eq(reverse_bytes(sink.dat[32:])),
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source.be.eq(reverse_bits(sink.be[4:])),
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source.be.eq(freversed(sink.be[4:])),
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If(source.stb & source.ack & source.eop,
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NextState("HEADER1")
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)
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@ -116,7 +106,7 @@ class Depacketizer(Module):
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dispatch_source.eop.eq(header_extracter.source.eop),
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dispatch_source.dat.eq(header_extracter.source.dat),
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dispatch_source.be.eq(header_extracter.source.be),
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_decode_header(tlp_common_header, header, dispatch_source)
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tlp_common_header.decode(header, dispatch_source)
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]
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self.submodules.dispatcher = Dispatcher(dispatch_source, dispatch_sinks)
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@ -132,7 +122,7 @@ class Depacketizer(Module):
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# decode TLP request and format local request
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tlp_req = Source(tlp_request_layout(dw))
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self.comb += Record.connect(dispatch_sinks[0], tlp_req)
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self.comb += _decode_header(tlp_request_header, header, tlp_req)
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self.comb += tlp_request_header.decode(header, tlp_req)
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req_source = self.req_source
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self.comb += [
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@ -151,7 +141,7 @@ class Depacketizer(Module):
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# decode TLP completion and format local completion
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tlp_cmp = Source(tlp_completion_layout(dw))
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self.comb += Record.connect(dispatch_sinks[1], tlp_cmp)
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self.comb += _decode_header(tlp_completion_header, header, tlp_cmp)
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self.comb += tlp_completion_header.decode(header, tlp_cmp)
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cmp_source = self.cmp_source
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self.comb += [
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@ -4,16 +4,6 @@ from migen.genlib.fsm import FSM, NextState
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from migen.genlib.misc import chooser
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from misoclib.com.litepcie.core.packet.common import *
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from misoclib.com.litepcie.core.switch.arbiter import Arbiter
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def _encode_header(h_dict, h_signal, obj):
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r = []
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for k, v in sorted(h_dict.items()):
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start = v.word*32+v.offset
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end = start+v.width
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r.append(h_signal[start:end].eq(getattr(obj, k)))
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return r
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class HeaderInserter(Module):
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@ -53,7 +43,7 @@ class HeaderInserter(Module):
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source.sop.eq(0),
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source.eop.eq(sink.eop),
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source.dat.eq(Cat(sink.header[64:96], reverse_bytes(sink.dat[:32]))),
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source.be.eq(Cat(Signal(4, reset=0xf), reverse_bits(sink.be[:4]))),
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source.be.eq(Cat(Signal(4, reset=0xf), freversed(sink.be[:4]))),
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If(source.stb & source.ack,
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sink.ack.eq(1),
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If(source.eop,
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@ -135,7 +125,7 @@ class Packetizer(Module):
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tlp_req.ack.eq(tlp_raw_req.ack),
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tlp_raw_req.sop.eq(tlp_req.sop),
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tlp_raw_req.eop.eq(tlp_req.eop),
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_encode_header(tlp_request_header, tlp_raw_req.header, tlp_req),
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tlp_request_header.encode(tlp_req, tlp_raw_req.header),
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tlp_raw_req.dat.eq(tlp_req.dat),
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tlp_raw_req.be.eq(tlp_req.be),
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]
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@ -179,7 +169,7 @@ class Packetizer(Module):
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tlp_cmp.ack.eq(tlp_raw_cmp.ack),
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tlp_raw_cmp.sop.eq(tlp_cmp.sop),
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tlp_raw_cmp.eop.eq(tlp_cmp.eop),
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_encode_header(tlp_completion_header, tlp_raw_cmp.header, tlp_cmp),
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tlp_completion_header.encode(tlp_cmp, tlp_raw_cmp.header),
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tlp_raw_cmp.dat.eq(tlp_cmp.dat),
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tlp_raw_cmp.be.eq(tlp_cmp.be),
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]
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@ -1,25 +0,0 @@
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from migen.fhdl.std import *
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from migen.genlib.roundrobin import *
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from migen.genlib.record import *
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class Arbiter(Module):
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def __init__(self, sources, sink):
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if len(sources) == 0:
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pass
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else:
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self.submodules.rr = RoundRobin(len(sources))
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self.grant = self.rr.grant
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cases = {}
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for i, source in enumerate(sources):
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sop = Signal()
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eop = Signal()
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ongoing = Signal()
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self.comb += [
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sop.eq(source.stb & source.sop),
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eop.eq(source.stb & source.eop & source.ack),
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]
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self.sync += ongoing.eq((sop | ongoing) & ~eop)
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self.comb += self.rr.request[i].eq((sop | ongoing) & ~eop)
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cases[i] = [Record.connect(source, sink)]
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self.comb += Case(self.grant, cases)
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@ -3,8 +3,6 @@ from migen.bank.description import *
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from misoclib.com.litepcie.common import *
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from misoclib.com.litepcie.core.switch.common import *
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from misoclib.com.litepcie.core.switch.arbiter import Arbiter
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from misoclib.com.litepcie.core.switch.dispatcher import Dispatcher
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from misoclib.com.litepcie.core.switch.request_controller import RequestController
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@ -1,40 +0,0 @@
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from migen.fhdl.std import *
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from migen.genlib.record import *
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class Dispatcher(Module):
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def __init__(self, source, sinks, one_hot=False):
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if len(sinks) == 0:
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self.sel = Signal()
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elif len(sinks) == 1:
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self.comb += Record.connect(source, sinks[0])
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self.sel = Signal()
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else:
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if one_hot:
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self.sel = Signal(len(sinks))
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else:
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self.sel = Signal(max=len(sinks))
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###
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sop = Signal()
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self.comb += sop.eq(source.stb & source.sop)
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sel = Signal(flen(self.sel))
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sel_r = Signal(flen(self.sel))
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self.sync += \
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If(sop,
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sel_r.eq(self.sel)
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)
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self.comb += \
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If(sop,
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sel.eq(self.sel)
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).Else(
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sel.eq(sel_r)
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)
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cases = {}
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for i, sink in enumerate(sinks):
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if one_hot:
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idx = 2**i
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else:
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idx = i
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cases[idx] = [Record.connect(source, sink)]
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cases["default"] = [source.ack.eq(1)]
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self.comb += Case(sel, cases)
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@ -13,9 +13,9 @@ def print_host(s):
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# Host model
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class Host(Module):
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def __init__(self, dw, root_id, endpoint_id, bar0_size=1*MB,
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phy_debug=False,
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chipset_debug=False, chipset_split=False, chipset_reordering=False,
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host_debug=False):
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phy_debug=False,
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chipset_debug=False, chipset_split=False, chipset_reordering=False,
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host_debug=False):
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self.debug = host_debug
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self.chipset_split = chipset_split
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###
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@ -4,7 +4,7 @@ from misoclib.com.litepcie.core.packet.common import *
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# TLP Layer model
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def get_field_data(field, dwords):
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return (dwords[field.word] >> field.offset) & (2**field.width-1)
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return (dwords[field.byte//4] >> field.offset) & (2**field.width-1)
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tlp_headers_dict = {
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"RD32": tlp_request_header,
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@ -23,14 +23,14 @@ class TLP():
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self.decode_dwords()
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def decode_dwords(self):
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for k, v in tlp_headers_dict[self.name].items():
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for k, v in tlp_headers_dict[self.name].fields.items():
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setattr(self, k, get_field_data(v, self.header))
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def encode_dwords(self, data=[]):
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self.header = [0, 0, 0]
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for k, v in tlp_headers_dict[self.name].items():
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field = tlp_headers_dict[self.name][k]
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self.header[field.word] |= (getattr(self, k) << field.offset)
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for k, v in tlp_headers_dict[self.name].fields.items():
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field = tlp_headers_dict[self.name].fields[k]
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self.header[field.byte//4] |= (getattr(self, k) << field.offset)
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self.data = data
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self.dwords = self.header + self.data
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return self.dwords
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@ -81,8 +81,8 @@ fmt_type_dict = {
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def parse_dwords(dwords):
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f = get_field_data(tlp_common_header["fmt"], dwords)
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t = get_field_data(tlp_common_header["type"], dwords)
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f = get_field_data(tlp_common_header.fields["fmt"], dwords)
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t = get_field_data(tlp_common_header.fields["type"], dwords)
|
||||
fmt_type = (f << 5) | t
|
||||
try:
|
||||
tlp, min_len = fmt_type_dict[fmt_type]
|
||||
|
|
|
|||
Loading…
Reference in a new issue