core/usb_ohci: fix SDRTristate clock
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@ -95,12 +95,14 @@ class USBOHCI(LiteXModule):
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o = usb_ios[i].dp_o,
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oe = usb_ios[i].dp_oe,
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i = usb_ios[i].dp_i,
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clk = ClockSignal("usb")
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)
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self.specials += SDRTristate(
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io = pads.dm[i],
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o = usb_ios[i].dm_o,
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oe = usb_ios[i].dm_oe,
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i = usb_ios[i].dm_i,
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clk = ClockSignal("usb")
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)
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self.add_sources(platform)
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