Hardware/litex
1
0
Fork 0
mirror of https://github.com/enjoy-digital/litex.git synced 2025-01-04 09:52:26 -05:00
Code Issues Projects Releases Packages Wiki Activity

add the possibility for a "precise" clock solution

Browse source 
If clocks and multipliers are planned well, we can have
a zero-error solution for clocks. Suggest to change < to <= in
margin comparison loop, so that a "perfect" solution is allowed
to converge.
This commit is contained in:
bunnie 2020-01-01 18:49:00 +08:00
parent 9336fe1139
commit 219bb7f294
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
litex/soc/cores/clock.py
View file

@ -74,7 +74,7 @@ class XilinxClocking(Module, AutoCSR):
valid = False
for d in range(*self.clkout_divide_range):
clk_freq = vco_freq/d
if abs(clk_freq - f) < f*m:
if abs(clk_freq - f) <= f*m:
config["clkout{}_freq".format(n)] = clk_freq
config["clkout{}_divide".format(n)] = d
config["clkout{}_phase".format(n)] = p