soc_core: declare csr address size when registering csr, fixes #212

2019-07-08 22:58:07 +02:00 · 2019-07-08 22:58:07 +02:00 · 21a5aaa4a6
parent 41b6fbde42
commit 21a5aaa4a6
1 changed files with 1 additions and 1 deletions
--- a/litex/soc/integration/soc_core.py
+++ b/litex/soc/integration/soc_core.py
@ -298,7 +298,7 @@ class SoCCore(Module):
        self.add_csr_master(self.wishbone2csr.csr)
        self.config["CSR_DATA_WIDTH"] = csr_data_width
        self.config["CSR_ALIGNMENT"] = csr_alignment
-        self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone)
+        self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))

        # Add UART
        if with_uart: