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soc_core: declare csr address size when registering csr, fixes #212

This commit is contained in:
Florent Kermarrec 2019-07-08 22:58:07 +02:00
parent 41b6fbde42
commit 21a5aaa4a6
1 changed files with 1 additions and 1 deletions
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2
litex/soc/integration/soc_core.py
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@ -298,7 +298,7 @@ class SoCCore(Module):
self.add_csr_master(self.wishbone2csr.csr) self.add_csr_master(self.wishbone2csr.csr)
self.config["CSR_DATA_WIDTH"] = csr_data_width self.config["CSR_DATA_WIDTH"] = csr_data_width
self.config["CSR_ALIGNMENT"] = csr_alignment self.config["CSR_ALIGNMENT"] = csr_alignment
self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone) self.register_mem("csr", self.soc_mem_map["csr"], self.wishbone2csr.wishbone, 2**(csr_address_width + 2))
# Add UART # Add UART
if with_uart: if with_uart: