Merge pull request #593 from antmicro/jboc/axi-lite
Add AXILite components: AXILiteSRAM and AXILite2CSR
This commit is contained in:
enjoy-digital
GitHub
commit
21c48eed76
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@ -280,21 +280,46 @@ class SoCBusHandler(Module):
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# Add Master/Slave -----------------------------------------------------------------------------
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def add_adapter(self, name, interface, direction="m2s"):
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assert direction in ["m2s", "s2m"]
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if interface.data_width != self.data_width:
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self.logger.info("{} Bus {} from {}-bit to {}-bit.".format(
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colorer(name),
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colorer("converted", color="cyan"),
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colorer(interface.data_width),
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colorer(self.data_width)))
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if isinstance(interface, wishbone.Interface):
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new_interface = wishbone.Interface(data_width=self.data_width)
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if direction == "m2s":
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converter = wishbone.Converter(master=interface, slave=new_interface)
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if direction == "s2m":
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converter = wishbone.Converter(master=new_interface, slave=interface)
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self.submodules += converter
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return new_interface
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elif isinstance(interface, axi.AXILiteInterface):
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# Data width conversion
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intermediate = axi.AXILiteInterface(data_width=self.data_width)
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if direction == "m2s":
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converter = axi.AXILiteConverter(master=interface, slave=intermediate)
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if direction == "s2m":
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converter = axi.AXILiteConverter(master=intermediate, slave=interface)
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self.submodules += converter
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# Bus type conversion
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new_interface = wishbone.Interface(data_width=self.data_width)
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if direction == "m2s":
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converter = axi.AXILite2Wishbone(axi_lite=intermediate, wishbone=new_interface)
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elif direction == "s2m":
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converter = axi.Wishbone2AXILite(wishbone=new_interface, axi_lite=intermediate)
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self.submodules += converter
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else:
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return interface
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raise TypeError(interface)
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fmt = "{name} Bus {converted} from {frombus} {frombits}-bit to {tobus} {tobits}-bit."
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frombus = "Wishbone" if isinstance(interface, wishbone.Interface) else "AXILite"
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tobus = "Wishbone" if isinstance(new_interface, wishbone.Interface) else "AXILite"
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frombits = interface.data_width
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tobits = new_interface.data_width
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if frombus != tobus or frombits != tobits:
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self.logger.info(fmt.format(
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name = colorer(name),
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converted = colorer("converted", color="cyan"),
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frombus = colorer("Wishbone" if isinstance(interface, wishbone.Interface) else "AXILite"),
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frombits = colorer(interface.data_width),
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tobus = colorer("Wishbone" if isinstance(new_interface, wishbone.Interface) else "AXILite"),
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tobits = colorer(new_interface.data_width)))
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return new_interface
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def add_master(self, name=None, master=None):
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if name is None:
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@ -55,6 +55,23 @@ def r_description(data_width, id_width):
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("id", id_width)
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]
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def _connect_axi(master, slave):
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channel_modes = {
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"aw": "master",
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"w" : "master",
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"b" : "slave",
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"ar": "master",
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"r" : "slave",
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}
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r = []
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for channel, mode in channel_modes.items():
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if mode == "master":
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m, s = getattr(master, channel), getattr(slave, channel)
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else:
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s, m = getattr(master, channel), getattr(slave, channel)
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r.extend(m.connect(s))
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return r
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class AXIInterface:
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def __init__(self, data_width=32, address_width=32, id_width=1, clock_domain="sys"):
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self.data_width = data_width
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@ -68,6 +85,9 @@ class AXIInterface:
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self.ar = stream.Endpoint(ax_description(address_width, id_width))
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self.r = stream.Endpoint(r_description(data_width, id_width))
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def connect(self, slave):
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return _connect_axi(self, slave)
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# AXI Lite Definition ------------------------------------------------------------------------------
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def ax_lite_description(address_width):
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@ -138,6 +158,45 @@ class AXILiteInterface:
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r.append(pad.eq(sig))
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return r
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def connect(self, slave):
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return _connect_axi(self, slave)
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def write(self, addr, data, strb=None):
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if strb is None:
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strb = 2**len(self.w.strb) - 1
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yield self.aw.valid.eq(1)
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yield self.aw.addr.eq(addr)
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yield self.w.data.eq(data)
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yield self.w.valid.eq(1)
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yield self.w.strb.eq(strb)
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yield
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while not (yield self.aw.ready):
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yield
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while not (yield self.w.ready):
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yield
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while not (yield self.b.valid):
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yield
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yield self.b.ready.eq(1)
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resp = (yield self.b.resp)
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yield
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yield self.b.ready.eq(0)
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return resp
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def read(self, addr):
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yield self.ar.valid.eq(1)
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yield self.ar.addr.eq(addr)
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yield
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while not (yield self.ar.ready):
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yield
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while not (yield self.r.valid):
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yield
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yield self.r.ready.eq(1)
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data = (yield self.r.data)
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resp = (yield self.r.resp)
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yield
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yield self.r.ready.eq(0)
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return (data, resp)
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# AXI Stream Definition ----------------------------------------------------------------------------
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class AXIStreamInterface(stream.Endpoint):
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@ -494,3 +553,145 @@ class Wishbone2AXILite(Module):
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wishbone.err.eq(1),
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NextState("IDLE")
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)
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# AXILite to CSR -----------------------------------------------------------------------------------
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def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=None):
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"""Connection of AXILite to simple bus with 1-cycle latency, such as CSR bus or Memory port"""
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bus_data_width = axi_lite.data_width
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adr_shift = log2_int(bus_data_width//8)
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do_read = Signal()
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do_write = Signal()
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last_was_read = Signal()
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comb = []
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if port_dat_w is not None:
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comb.append(port_dat_w.eq(axi_lite.w.data))
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if port_we is not None:
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if len(port_we) > 1:
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for i in range(bus_data_width//8):
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comb.append(port_we[i].eq(axi_lite.w.valid & axi_lite.w.ready & axi_lite.w.strb[i]))
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else:
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comb.append(port_we.eq(axi_lite.w.valid & axi_lite.w.ready & (axi_lite.w.strb != 0)))
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fsm = FSM()
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fsm.act("START-TRANSACTION",
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# If the last access was a read, do a write, and vice versa
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If(axi_lite.aw.valid & axi_lite.ar.valid,
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do_write.eq(last_was_read),
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do_read.eq(~last_was_read),
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).Else(
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do_write.eq(axi_lite.aw.valid),
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do_read.eq(axi_lite.ar.valid),
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),
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# Start reading/writing immediately not to waste a cycle
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If(do_write,
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port_adr.eq(axi_lite.aw.addr[adr_shift:]),
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If(axi_lite.w.valid,
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axi_lite.aw.ready.eq(1),
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axi_lite.w.ready.eq(1),
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NextState("SEND-WRITE-RESPONSE")
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)
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).Elif(do_read,
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port_adr.eq(axi_lite.ar.addr[adr_shift:]),
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axi_lite.ar.ready.eq(1),
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NextState("SEND-READ-RESPONSE"),
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)
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)
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fsm.act("SEND-READ-RESPONSE",
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NextValue(last_was_read, 1),
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# As long as we have correct address port.dat_r will be valid
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port_adr.eq(axi_lite.ar.addr[adr_shift:]),
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axi_lite.r.data.eq(port_dat_r),
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axi_lite.r.resp.eq(RESP_OKAY),
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axi_lite.r.valid.eq(1),
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If(axi_lite.r.ready,
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NextState("START-TRANSACTION")
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)
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)
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fsm.act("SEND-WRITE-RESPONSE",
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NextValue(last_was_read, 0),
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axi_lite.b.valid.eq(1),
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axi_lite.b.resp.eq(RESP_OKAY),
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If(axi_lite.b.ready,
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NextState("START-TRANSACTION")
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)
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)
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return fsm, comb
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class AXILite2CSR(Module):
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def __init__(self, axi_lite=None, csr=None):
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if axi_lite is None:
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axi_lite = AXILiteInterface()
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if csr is None:
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csr = csr.bus.Interface()
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self.axi_lite = axi_lite
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self.csr = csr
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fsm, comb = axi_lite_to_simple(self.axi_lite,
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port_adr=self.csr.adr, port_dat_r=self.csr.dat_r,
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port_dat_w=self.csr.dat_w, port_we=self.csr.we)
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self.submodules.fsm = fsm
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self.comb += comb
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# AXILite SRAM -------------------------------------------------------------------------------------
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class AXILiteSRAM(Module):
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def __init__(self, mem_or_size, read_only=None, init=None, bus=None):
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if bus is None:
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bus = AXILiteInterface()
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self.bus = bus
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bus_data_width = len(self.bus.r.data)
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if isinstance(mem_or_size, Memory):
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assert(mem_or_size.width <= bus_data_width)
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self.mem = mem_or_size
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else:
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self.mem = Memory(bus_data_width, mem_or_size//(bus_data_width//8), init=init)
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if read_only is None:
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if hasattr(self.mem, "bus_read_only"):
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read_only = self.mem.bus_read_only
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else:
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read_only = False
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###
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# Create memory port
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port = self.mem.get_port(write_capable=not read_only, we_granularity=8,
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mode=READ_FIRST if read_only else WRITE_FIRST)
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self.specials += self.mem, port
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# Generate write enable signal
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if not read_only:
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self.comb += port.dat_w.eq(self.bus.w.data),
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self.comb += [port.we[i].eq(self.bus.w.valid & self.bus.w.ready & self.bus.w.strb[i])
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for i in range(bus_data_width//8)]
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# Transaction logic
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fsm, comb = axi_lite_to_simple(self.bus,
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port_adr=port.adr, port_dat_r=port.dat_r,
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port_dat_w=port.dat_w if not read_only else None,
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port_we=port.we if not read_only else None)
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self.submodules.fsm = fsm
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self.comb += comb
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# AXILite Data Width Converter ---------------------------------------------------------------------
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class AXILiteConverter(Module):
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"""AXILite data width converter"""
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def __init__(self, master, slave):
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self.master = master
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self.slave = slave
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# # #
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dw_from = len(master.r.data)
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dw_to = len(slave.r.data)
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if dw_from > dw_to:
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raise NotImplementedError
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elif dw_from < dw_to:
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raise NotImplementedError
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else:
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self.comb += master.connect(slave)
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@ -7,7 +7,7 @@ import random
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from migen import *
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from litex.soc.interconnect.axi import *
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from litex.soc.interconnect import wishbone
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from litex.soc.interconnect import wishbone, csr_bus
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# Software Models ----------------------------------------------------------------------------------
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@ -358,5 +358,84 @@ class TestAXI(unittest.TestCase):
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dut.errors += 1
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dut = DUT()
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run_simulation(dut, [generator(dut)], vcd_name="toto.vcd")
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run_simulation(dut, [generator(dut)])
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self.assertEqual(dut.errors, 0)
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def test_axilite2csr(self):
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@passive
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def csr_mem_handler(csr, mem):
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while True:
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adr = (yield csr.adr)
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yield csr.dat_r.eq(mem[adr])
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if (yield csr.we):
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mem[adr] = (yield csr.dat_w)
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yield
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class DUT(Module):
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def __init__(self):
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self.axi_lite = AXILiteInterface()
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self.csr = csr_bus.Interface()
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self.submodules.axilite2csr = AXILite2CSR(self.axi_lite, self.csr)
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self.errors = 0
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prng = random.Random(42)
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mem_ref = [prng.randrange(255) for i in range(100)]
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def generator(dut):
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dut.errors = 0
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for adr, ref in enumerate(mem_ref):
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adr = adr << 2
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data, resp = (yield from dut.axi_lite.read(adr))
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self.assertEqual(resp, 0b00)
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if data != ref:
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dut.errors += 1
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write_data = [prng.randrange(255) for _ in mem_ref]
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for adr, wdata in enumerate(write_data):
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adr = adr << 2
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resp = (yield from dut.axi_lite.write(adr, wdata))
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self.assertEqual(resp, 0b00)
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rdata, resp = (yield from dut.axi_lite.read(adr))
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self.assertEqual(resp, 0b00)
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if rdata != wdata:
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dut.errors += 1
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dut = DUT()
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mem = [v for v in mem_ref]
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run_simulation(dut, [generator(dut), csr_mem_handler(dut.csr, mem)])
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self.assertEqual(dut.errors, 0)
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def test_axilite_sram(self):
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class DUT(Module):
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def __init__(self, size, init):
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self.axi_lite = AXILiteInterface()
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self.submodules.sram = AXILiteSRAM(size, init=init, bus=self.axi_lite)
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self.errors = 0
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def generator(dut, ref_init):
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for adr, ref in enumerate(ref_init):
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adr = adr << 2
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data, resp = (yield from dut.axi_lite.read(adr))
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self.assertEqual(resp, 0b00)
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if data != ref:
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dut.errors += 1
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write_data = [prng.randrange(255) for _ in ref_init]
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for adr, wdata in enumerate(write_data):
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adr = adr << 2
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resp = (yield from dut.axi_lite.write(adr, wdata))
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self.assertEqual(resp, 0b00)
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rdata, resp = (yield from dut.axi_lite.read(adr))
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self.assertEqual(resp, 0b00)
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if rdata != wdata:
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dut.errors += 1
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prng = random.Random(42)
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init = [prng.randrange(2**32) for i in range(100)]
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dut = DUT(size=len(init)*4, init=[v for v in init])
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run_simulation(dut, [generator(dut, init)])
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self.assertEqual(dut.errors, 0)
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