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tools/litex_sim: Avoid use of SoCCore.add_memory_region/add_wb_slave.

This commit is contained in:
Florent Kermarrec 2022-11-03 19:22:26 +01:00
parent 964c82e4e8
commit 21e46b6b6c
1 changed files with 6 additions and 4 deletions
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10
litex/tools/litex_sim.py
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@ -227,8 +227,9 @@ class SimSoC(SoCCore):
hw_mac = etherbone_mac_address)
# SoftCPU
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), 0x2000, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, self.ethmac.bus, 0x2000)
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)
# HW ethernet
@ -248,9 +249,10 @@ class SimSoC(SoCCore):
dw = 64 if ethernet_phy_model == "xgmii" else 32,
interface = "wishbone",
endianness = self.cpu.endianness)
# Compute Regions size and add it to the SoC.
ethmac_region_size = (ethmac.rx_slots.constant + ethmac.tx_slots.constant)*ethmac.slot_size.constant
self.add_memory_region("ethmac", self.mem_map.get("ethmac", None), ethmac_region_size, type="io")
self.add_wb_slave(self.mem_regions["ethmac"].origin, ethmac.bus, ethmac_region_size)
ethmac_region = SoCRegion(origin=self.mem_map.get("ethmac", None), size=ethmac_region_size, cached=False)
self.bus.add_slave(name="ethmac", slave=ethmac.bus, region=ethmac_region)
if self.irq.enabled:
self.irq.add("ethmac", use_loc_if_exists=True)