soc/interconnect/stream: fix merge issue (missing params connect)
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6c71811138
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2218ece98a
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@ -59,10 +59,10 @@ class Endpoint(Record):
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class Source(Endpoint):
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pass
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pass
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class Sink(Endpoint):
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pass
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pass
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class _FIFOWrapper(Module):
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@ -256,8 +256,8 @@ class Buffer(PipelinedActor):
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PipelinedActor.__init__(self, 1)
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self.sync += \
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If(self.pipe_ce,
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self.source.payload.eq(self.sink.payload),
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self.source.param.eq(self.sink.param)
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self.source.payload.eq(self.sink.payload),
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self.source.param.eq(self.sink.param)
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)
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@ -315,6 +315,11 @@ class Unpack(Module):
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cases[i] = [source.payload.raw_bits().eq(getattr(sink.payload, "chunk"+str(chunk)).raw_bits())]
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self.comb += Case(mux, cases).makedefault()
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for f in description_from.param_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst.eq(src)
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if description_from.packetized:
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self.comb += [
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source.sop.eq(sink.sop & first),
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@ -347,6 +352,11 @@ class Pack(Module):
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load_part.eq(sink.stb & sink.ack)
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]
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for f in description_to.param_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(self.source, f[0])
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self.sync += If(load_part, dst.eq(src))
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if description_to.packetized:
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demux_last = ((demux == (n - 1)) | sink.eop)
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else:
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@ -397,6 +407,11 @@ class Chunkerize(CombinatorialActor):
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dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0])
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self.comb += dst.eq(src[i*len(src)//n:(i+1)*len(src)//n])
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for f in self.sink.description.param_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst.eq(src)
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class Unchunkerize(CombinatorialActor):
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def __init__(self, layout_from, n, layout_to, reverse=False):
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@ -420,6 +435,11 @@ class Unchunkerize(CombinatorialActor):
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dst = getattr(self.source, f[0])
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self.comb += dst[i*len(dst)//n:(i+1)*len(dst)//n].eq(src)
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for f in self.sink.description.param_layout:
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src = getattr(self.sink, f[0])
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dst = getattr(self.source, f[0])
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self.comb += dst.eq(src)
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class Converter(Module):
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def __init__(self, layout_from, layout_to, reverse=False):
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@ -440,9 +460,9 @@ class Converter(Module):
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self.submodules.unpack = Unpack(ratio, layout_to)
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self.submodules += Pipeline(self.sink,
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self.chunkerize,
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self.unpack,
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self.source)
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self.chunkerize,
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self.unpack,
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self.source)
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# upconverter
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elif width_to > width_from:
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if width_to % width_from:
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@ -452,8 +472,8 @@ class Converter(Module):
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self.submodules.unchunkerize = Unchunkerize(layout_from, ratio, layout_to, reverse)
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self.submodules += Pipeline(self.sink,
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self.pack,
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self.unchunkerize,
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self.pack,
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self.unchunkerize,
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self.source)
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# direct connection
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else:
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