soc/interconnect/stream: fix merge issue (missing params connect)

This commit is contained in:
Florent Kermarrec 2016-02-01 00:08:27 +01:00
parent 6c71811138
commit 2218ece98a
1 changed files with 29 additions and 9 deletions

View File

@ -315,6 +315,11 @@ class Unpack(Module):
cases[i] = [source.payload.raw_bits().eq(getattr(sink.payload, "chunk"+str(chunk)).raw_bits())] cases[i] = [source.payload.raw_bits().eq(getattr(sink.payload, "chunk"+str(chunk)).raw_bits())]
self.comb += Case(mux, cases).makedefault() self.comb += Case(mux, cases).makedefault()
for f in description_from.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)
if description_from.packetized: if description_from.packetized:
self.comb += [ self.comb += [
source.sop.eq(sink.sop & first), source.sop.eq(sink.sop & first),
@ -347,6 +352,11 @@ class Pack(Module):
load_part.eq(sink.stb & sink.ack) load_part.eq(sink.stb & sink.ack)
] ]
for f in description_to.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.sync += If(load_part, dst.eq(src))
if description_to.packetized: if description_to.packetized:
demux_last = ((demux == (n - 1)) | sink.eop) demux_last = ((demux == (n - 1)) | sink.eop)
else: else:
@ -397,6 +407,11 @@ class Chunkerize(CombinatorialActor):
dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0]) dst = getattr(getattr(self.source, "chunk"+str(chunk)), f[0])
self.comb += dst.eq(src[i*len(src)//n:(i+1)*len(src)//n]) self.comb += dst.eq(src[i*len(src)//n:(i+1)*len(src)//n])
for f in self.sink.description.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)
class Unchunkerize(CombinatorialActor): class Unchunkerize(CombinatorialActor):
def __init__(self, layout_from, n, layout_to, reverse=False): def __init__(self, layout_from, n, layout_to, reverse=False):
@ -420,6 +435,11 @@ class Unchunkerize(CombinatorialActor):
dst = getattr(self.source, f[0]) dst = getattr(self.source, f[0])
self.comb += dst[i*len(dst)//n:(i+1)*len(dst)//n].eq(src) self.comb += dst[i*len(dst)//n:(i+1)*len(dst)//n].eq(src)
for f in self.sink.description.param_layout:
src = getattr(self.sink, f[0])
dst = getattr(self.source, f[0])
self.comb += dst.eq(src)
class Converter(Module): class Converter(Module):
def __init__(self, layout_from, layout_to, reverse=False): def __init__(self, layout_from, layout_to, reverse=False):