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report cachesize in wishbone2lasmi

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Florent Kermarrec 2015-02-27 14:12:13 +01:00
parent 54a8a52e90
commit 225a2d4704
1 changed files with 3 additions and 1 deletions
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4
migen/bus/wishbone2lasmi.py
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@ -1,12 +1,14 @@
from migen.fhdl.std import * from migen.fhdl.std import *
from migen.bus import wishbone from migen.bus import wishbone
from migen.bank.description import *
from migen.genlib.fsm import FSM, NextState from migen.genlib.fsm import FSM, NextState
from migen.genlib.misc import split, displacer, chooser from migen.genlib.misc import split, displacer, chooser
from migen.genlib.record import Record, layout_len from migen.genlib.record import Record, layout_len
# cachesize (in 32-bit words) is the size of the data store, must be a power of 2 # cachesize (in 32-bit words) is the size of the data store, must be a power of 2
class WB2LASMI(Module): class WB2LASMI(Module, AutoCSR):
def __init__(self, cachesize, lasmim): def __init__(self, cachesize, lasmim):
self._cachesize = CSRStatus(8, reset=log2_int(cachesize))
self.wishbone = wishbone.Interface() self.wishbone = wishbone.Interface()
### ###