tools/litex_client: add --read/--write args to do simple MMAP accesses to SoC bus.

ex reading/writing to scratch register over jtagbone:

In the SoC:
self.add_jtagbone()

Open LiteX Server:
litex_server --jtag

Do the MMAP accesses:
./litex_cli --read 0x4
0x12345678
./litex_clk --write 0x4 0x5aa55aa5
./litex_cli --read 0x4
0x5aa55aa5

litex/tools/litex_client.py

@@ -111,13 +111,31 @@ def dump_registers(port):
 
     wb.close()
 
+def read_memory(port, addr):
+    wb = RemoteClient(port=port)
+    wb.open()
+
+    print("0x{:08x}".format(wb.read(addr)))
+
+    wb.close()
+
+def write_memory(port, addr, data):
+    wb = RemoteClient(port=port)
+    wb.open()
+
+    wb.write(addr, data)
+
+    wb.close()
+
 # Run ----------------------------------------------------------------------------------------------
 
 def main():
     parser = argparse.ArgumentParser(description="LiteX Client utility")
     parser.add_argument("--port",  default="1234",        help="Host bind port")
-    parser.add_argument("--ident", action="store_true", help="Dump FPGA identifier")
-    parser.add_argument("--regs",  action="store_true", help="Dump FPGA registers")
+    parser.add_argument("--ident", action="store_true",   help="Dump SoC identifier")
+    parser.add_argument("--regs",  action="store_true",   help="Dump SoC registers")
+    parser.add_argument("--read",  default=None,          help="Do a MMAP Read to SoC bus (--read addr)")
+    parser.add_argument("--write", default=None, nargs=2, help="Do a MMAP Write to SoC bus (--write addr data)")
     args = parser.parse_args()
 
     port = int(args.port, 0)
@@ -128,5 +146,11 @@ def main():
     if args.regs:
         dump_registers(port=port)
 
+    if args.read:
+        read_memory(port=port, addr=int(args.read, 0))
+
+    if args.write:
+        write_memory(port=port, addr=int(args.write[0], 0), data=int(args.write[1], 0))
+
 if __name__ == "__main__":
     main()