cpu/gowin_emcu: Minor cosmetic cleanups, add copyright.
This commit is contained in:
Florent Kermarrec
parent
7286f95f55
commit
230ba5f7ba
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@ -1,42 +1,51 @@
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#
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# This file is part of LiteX.
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#
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# Copyright (c) 2021 Ilia Sergachev <ilia.sergachev@protonmail.ch>
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# SPDX-License-Identifier: BSD-2-Clause
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from migen import *
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from litex.soc.interconnect import wishbone, ahb
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from litex.soc.cores.cpu import CPU
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# AHB Flash ----------------------------------------------------------------------------------------
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class AHBFlash(Module):
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def __init__(self, bus):
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addr = Signal(13)
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read_enable = Signal()
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read = Signal()
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self.comb += bus.resp.eq(0)
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self.submodules.fsm = fsm = FSM()
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fsm.act("IDLE",
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bus.readyout.eq(1),
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If(bus.sel & bus.trans[1],
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NextValue(addr, bus.addr[2:]),
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NextState('READ'),
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NextState("READ"),
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)
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)
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fsm.act("READ",
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read_enable.eq(1),
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NextState('WAIT'),
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read.eq(1),
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NextState("WAIT"),
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)
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fsm.act('WAIT',
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NextState('IDLE')
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fsm.act("WAIT",
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NextState("IDLE")
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)
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self.specials += Instance(
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'FLASH256K',
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self.specials += Instance("FLASH256K",
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o_DOUT = bus.rdata,
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i_DIN = Signal(32),
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i_XADR = addr[6:],
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i_YADR = addr[:6],
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i_XE=~ResetSignal(),
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i_YE=~ResetSignal(),
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i_SE=read_enable,
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i_XE = ~ResetSignal("sys"),
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i_YE = ~ResetSignal("sys"),
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i_SE = read,
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i_PROG = 0,
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i_ERASE = 0,
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i_NVSTR = 0
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)
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# Gowin EMCU ---------------------------------------------------------------------------------------
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class GowinEMCU(CPU):
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variants = ["standard"]
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@ -46,11 +55,14 @@ class GowinEMCU(CPU):
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data_width = 32
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endianness = "little"
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gcc_triple = "arm-none-eabi"
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gcc_flags = '-mcpu=cortex-m3 -mthumb'
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gcc_flags = "-mcpu=cortex-m3 -mthumb"
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linker_output_format = "elf32-littlearm"
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nop = "nop"
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io_regions = {0x4000_0000: 0x2000_0000,
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0xA000_0000: 0x6000_0000} # Origin, Length.
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io_regions = {
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# Origin, Length.
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0x4000_0000: 0x2000_0000,
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0xa000_0000: 0x6000_0000
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}
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@property
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def mem_map(self):
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@ -62,12 +74,13 @@ class GowinEMCU(CPU):
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def __init__(self, platform, variant, *args, **kwargs):
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super().__init__(*args, **kwargs)
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self.reset = Signal()
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self.bus_reset = Signal()
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bus_reset_n = Signal()
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self.comb += self.bus_reset.eq(~bus_reset_n)
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self.interrupt = Signal(5)
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self.reset_address = self.mem_map['rom'] + 0
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self.reset_address = self.mem_map["rom"] + 0
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self.gpio_in = Signal(16)
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self.gpio_out = Signal(16)
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@ -81,7 +94,7 @@ class GowinEMCU(CPU):
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i_FLASHERR = Signal(),
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i_FLASHINT = Signal(),
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i_FCLK=ClockSignal(),
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i_FCLK = ClockSignal("sys"),
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i_PORESETN = ~self.reset,
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i_SYSRESETN = ~self.reset,
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i_RTCSRCCLK = Signal(), # TODO - RTC clk in
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@ -114,12 +127,11 @@ class GowinEMCU(CPU):
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)
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for i in range(n_srams):
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self.specials += Instance(
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'SDPB',
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self.specials += Instance("SDPB",
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p_READ_MODE = 0,
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p_BIT_WIDTH_0 = single_sram_dw,
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p_BIT_WIDTH_1 = single_sram_dw,
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p_RESET_MODE='SYNC',
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p_RESET_MODE = "SYNC",
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p_BLK_SEL_0 = 0b111,
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p_BLK_SEL_1 = 0b111,
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o_DO = Cat(sram0_rdata[i * single_sram_dw: (i + 1) * single_sram_dw], Signal(sram_dw - single_sram_dw)),
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@ -141,11 +153,11 @@ class GowinEMCU(CPU):
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ahb_flash = ahb.Interface()
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for s, _ in ahb_flash.master_signals:
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if s in ['wdata', 'write', 'mastlock', 'prot']:
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if s in ["wdata", "write", "mastlock", "prot"]:
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continue
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self.cpu_params[f'o_TARGFLASH0H{s.upper()}'] = getattr(ahb_flash, s)
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self.cpu_params[f"o_TARGFLASH0H{s.upper()}"] = getattr(ahb_flash, s)
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for s, _ in ahb_flash.slave_signals:
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self.cpu_params[f'i_TARGFLASH0H{s.upper()}'] = getattr(ahb_flash, s)
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self.cpu_params[f"i_TARGFLASH0H{s.upper()}"] = getattr(ahb_flash, s)
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flash = ResetInserter()(AHBFlash(ahb_flash))
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self.comb += flash.reset.eq(self.bus_reset)
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self.submodules += flash
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@ -157,19 +169,19 @@ class GowinEMCU(CPU):
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ahb_targexp0 = ahb.Interface()
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for s, _ in ahb_targexp0.master_signals:
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# TODO: due to unexpected writes by the CPU bus is currently forced read-only
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if s == 'write':
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if s == "write":
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continue
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self.cpu_params[f'o_TARGEXP0H{s.upper()}'] = getattr(ahb_targexp0, s)
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self.cpu_params[f"o_TARGEXP0H{s.upper()}"] = getattr(ahb_targexp0, s)
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for s, _ in ahb_targexp0.slave_signals:
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self.cpu_params[f'i_TARGEXP0H{s.upper()}'] = getattr(ahb_targexp0, s)
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self.cpu_params[f"i_TARGEXP0H{s.upper()}"] = getattr(ahb_targexp0, s)
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self.submodules += ahb.AHB2Wishbone(ahb_targexp0, self.pbus)
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def connect_uart(self, pads, n=0):
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assert n in (0, 1), "this CPU has 2 built-in UARTs, 0 and 1"
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self.cpu_params.update({
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f'i_UART{n}RXDI': pads.rx,
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f'o_UART{n}TXDO': pads.tx,
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f'o_UART{n}BAUDTICK': Signal()
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f"i_UART{n}RXDI": pads.rx,
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f"o_UART{n}TXDO": pads.tx,
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f"o_UART{n}BAUDTICK": Signal()
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})
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def connect_jtag(self, pads):
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@ -180,7 +192,7 @@ class GowinEMCU(CPU):
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o_DAPNTDOEN = Signal(),
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i_DAPNTRST = ~self.reset,
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i_DAPSWCLKTCK = pads.tck,
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o_DAPJTAGNSW=Signal(), # indicates debug mode, JTAG or SWD
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o_DAPJTAGNSW = Signal(), # Indicates debug mode, JTAG or SWD
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)
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def do_finalize(self):
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