liteeth/phy/gmii : set tx_er to 0 only if it exits
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@ -7,8 +7,9 @@ class LiteEthPHYGMIITX(Module):
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def __init__(self, pads):
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def __init__(self, pads):
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self.sink = sink = Sink(eth_phy_description(8))
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self.sink = sink = Sink(eth_phy_description(8))
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###
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###
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if hasattr(pads, "tx_er"):
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self.sync += pads.tx_er.eq(0)
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self.sync += [
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self.sync += [
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pads.tx_er.eq(0),
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pads.tx_en.eq(sink.stb),
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pads.tx_en.eq(sink.stb),
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pads.tx_data.eq(sink.data)
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pads.tx_data.eq(sink.data)
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]
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]
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