build: automatically add keep attribute to signals with timing constraints.

Avoid having to specify it manually or eventually forget to do it and have a constraints that is not applied correctly.

litex/build/altera/quartus.py

@@ -225,11 +225,14 @@ class AlteraQuartusToolchain:
         return v_output.ns
 
     def add_period_constraint(self, platform, clk, period):
+        clk.attr.add("keep")
         if clk in self.clocks:
             raise ValueError("A period constraint already exists")
         period = math.floor(period*1e3)/1e3 # Round to lowest picosecond
         self.clocks[clk] = period
 
     def add_false_path_constraint(self, platform, from_, to):
+        from_.attr.add("keep")
+        to.attr.add("keep")
         if (to, from_) not in self.false_paths:
             self.false_paths.add((from_, to))

litex/build/lattice/diamond.py

@@ -194,6 +194,7 @@ class LatticeDiamondToolchain:
         return v_output.ns
 
     def add_period_constraint(self, platform, clk, period):
+        clk.attr.add("keep")
         # TODO: handle differential clk
         platform.add_platform_command("""FREQUENCY PORT "{clk}" {freq} MHz;""".format(
             freq=str(float(1/period)*1000), clk="{clk}"), clk=clk)

litex/build/lattice/icestorm.py

@@ -231,8 +231,8 @@ class LatticeIceStormToolchain:
         return "\n".join(read_files)
 
     def add_period_constraint(self, platform, clk, period):
+        clk.attr.add("keep")
         new_freq = 1000.0/period
-
         if clk not in self.freq_constraints.keys():
             self.freq_constraints[clk] = new_freq
         else:

litex/build/microsemi/platform.py

@@ -28,6 +28,7 @@ class MicrosemiPlatform(GenericPlatform):
         return self.toolchain.build(self, *args, **kwargs)
 
     def add_period_constraint(self, clk, period):
+        clk.attr.add("keep")
         if hasattr(clk, "p"):
             clk = clk.p
         self.toolchain.add_period_constraint(self, clk, period)
@@ -37,4 +38,6 @@ class MicrosemiPlatform(GenericPlatform):
             from_ = from_.p
         if hasattr(to, "p"):
             to = to.p
+        from_.attr.add("keep")
+        to.attr.add("keep")
         self.toolchain.add_false_path_constraint(self, from_, to)

litex/build/xilinx/ise.py

@@ -249,6 +249,7 @@ class XilinxISEToolchain:
     # them through clock objects like DCM and PLL objects.
 
     def add_period_constraint(self, platform, clk, period):
+        clk.attr.add("keep")
         platform.add_platform_command(
             """
 NET "{clk}" TNM_NET = "PRD{clk}";
@@ -258,6 +259,8 @@ TIMESPEC "TS{clk}" = PERIOD "PRD{clk}" """ + str(period) + """ ns HIGH 50%;
             )
 
     def add_false_path_constraint(self, platform, from_, to):
+        from_.attr.add("keep")
+        to.attr.add("keep")
         platform.add_platform_command(
             """
 NET "{from_}" TNM_NET = "TIG{from_}";

litex/build/xilinx/vivado.py

@@ -269,12 +269,15 @@ class XilinxVivadoToolchain:
         return v_output.ns
 
     def add_period_constraint(self, platform, clk, period):
+        clk.attr.add("keep")
         if clk in self.clocks:
             raise ValueError("A period constraint already exists")
         period = math.floor(period*1e3)/1e3 # round to lowest picosecond
         self.clocks[clk] = period
 
     def add_false_path_constraint(self, platform, from_, to):
+        from_.attr.add("keep")
+        to.attr.add("keep")
         if (to, from_) not in self.false_paths:
             self.false_paths.add((from_, to))