soc/builder: Propagate data_width to get_mem_data.
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@ -287,7 +287,10 @@ class Builder:
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def _initialize_rom_software(self):
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def _initialize_rom_software(self):
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# Get BIOS data from compiled BIOS binary.
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# Get BIOS data from compiled BIOS binary.
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bios_file = os.path.join(self.software_dir, "bios", "bios.bin")
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bios_file = os.path.join(self.software_dir, "bios", "bios.bin")
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bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu.endianness)
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bios_data = soc_core.get_mem_data(bios_file,
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data_width = self.soc.bus.data_width,
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endianness = self.soc.cpu.endianness,
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)
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# Initialize SoC with with BIOS data.
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# Initialize SoC with with BIOS data.
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self.soc.initialize_rom(bios_data)
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self.soc.initialize_rom(bios_data)
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@ -156,7 +156,10 @@ class SoCCore(LiteXSoC):
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# ROM.
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# ROM.
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# Initialize ROM from binary file when provided.
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# Initialize ROM from binary file when provided.
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if isinstance(integrated_rom_init, str):
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if isinstance(integrated_rom_init, str):
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integrated_rom_init = get_mem_data(integrated_rom_init, "little") # FIXME: Endianness.
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integrated_rom_init = get_mem_data(integrated_rom_init,
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endianness = "little", # FIXME: Depends on CPU.
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data_width = bus_data_width
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)
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integrated_rom_size = 4*len(integrated_rom_init)
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integrated_rom_size = 4*len(integrated_rom_init)
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# Disable ROM when no CPU/hard-CPU.
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# Disable ROM when no CPU/hard-CPU.
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@ -403,7 +403,8 @@ def main():
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# Configuration --------------------------------------------------------------------------------
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# Configuration --------------------------------------------------------------------------------
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cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
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cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
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bus_data_width = int(soc_kwargs["bus_data_width"])
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# UART.
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# UART.
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if soc_kwargs["uart_name"] == "serial":
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if soc_kwargs["uart_name"] == "serial":
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@ -412,7 +413,10 @@ def main():
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# ROM.
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# ROM.
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if args.rom_init:
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if args.rom_init:
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soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, endianness=cpu.endianness)
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soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init,
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data_width = bus_data_width,
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endianness = cpu.endianness
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)
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# RAM / SDRAM.
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# RAM / SDRAM.
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ram_boot_offset = 0x40000000 # FIXME
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ram_boot_offset = 0x40000000 # FIXME
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@ -420,8 +424,12 @@ def main():
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soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
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soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
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if args.integrated_main_ram_size:
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if args.integrated_main_ram_size:
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if args.ram_init is not None:
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if args.ram_init is not None:
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soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, endianness=cpu.endianness, offset=ram_boot_offset)
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soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init,
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ram_boot_address = get_boot_address(args.ram_init)
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data_width = bus_data_width,
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endianness = cpu.endianness,
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offset = ram_boot_offset
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)
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ram_boot_address = get_boot_address(args.ram_init)
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elif args.with_sdram:
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elif args.with_sdram:
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assert args.ram_init is None
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assert args.ram_init is None
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soc_kwargs["sdram_module"] = args.sdram_module
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soc_kwargs["sdram_module"] = args.sdram_module
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@ -430,7 +438,11 @@ def main():
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if args.sdram_from_spd_dump:
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if args.sdram_from_spd_dump:
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soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(args.sdram_from_spd_dump)
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soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(args.sdram_from_spd_dump)
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if args.sdram_init is not None:
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if args.sdram_init is not None:
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soc_kwargs["sdram_init"] = get_mem_data(args.sdram_init, endianness=cpu.endianness, offset=ram_boot_offset)
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soc_kwargs["sdram_init"] = get_mem_data(args.sdram_init,
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data_width = bus_data_width,
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endianness = cpu.endianness,
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offset = ram_boot_offset
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)
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ram_boot_address = get_boot_address(args.sdram_init)
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ram_boot_address = get_boot_address(args.sdram_init)
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# Ethernet.
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# Ethernet.
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