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soc/builder: Propagate data_width to get_mem_data.

This commit is contained in:
Florent Kermarrec 2022-09-12 16:46:20 +02:00
parent 481234de91
commit 23f529a313
3 changed files with 25 additions and 7 deletions
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5
litex/soc/integration/builder.py
View File

@ -287,7 +287,10 @@ class Builder:
def _initialize_rom_software(self):
# Get BIOS data from compiled BIOS binary.
bios_file = os.path.join(self.software_dir, "bios", "bios.bin")
bios_data = soc_core.get_mem_data(bios_file, self.soc.cpu.endianness)
bios_data = soc_core.get_mem_data(bios_file,
data_width = self.soc.bus.data_width,
endianness = self.soc.cpu.endianness,
)
# Initialize SoC with with BIOS data.
self.soc.initialize_rom(bios_data)

5
litex/soc/integration/soc_core.py
View File

@ -156,7 +156,10 @@ class SoCCore(LiteXSoC):
# ROM.
# Initialize ROM from binary file when provided.
if isinstance(integrated_rom_init, str):
integrated_rom_init = get_mem_data(integrated_rom_init, "little") # FIXME: Endianness.
integrated_rom_init = get_mem_data(integrated_rom_init,
endianness = "little", # FIXME: Depends on CPU.
data_width = bus_data_width
)
integrated_rom_size = 4*len(integrated_rom_init)
# Disable ROM when no CPU/hard-CPU.

22
litex/tools/litex_sim.py
View File

@ -403,7 +403,8 @@ def main():
# Configuration --------------------------------------------------------------------------------
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
cpu = CPUS.get(soc_kwargs.get("cpu_type", "vexriscv"))
bus_data_width = int(soc_kwargs["bus_data_width"])
# UART.
if soc_kwargs["uart_name"] == "serial":
@ -412,7 +413,10 @@ def main():
# ROM.
if args.rom_init:
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init, endianness=cpu.endianness)
soc_kwargs["integrated_rom_init"] = get_mem_data(args.rom_init,
data_width = bus_data_width,
endianness = cpu.endianness
)
# RAM / SDRAM.
ram_boot_offset = 0x40000000 # FIXME
@ -420,8 +424,12 @@ def main():
soc_kwargs["integrated_main_ram_size"] = args.integrated_main_ram_size
if args.integrated_main_ram_size:
if args.ram_init is not None:
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init, endianness=cpu.endianness, offset=ram_boot_offset)
ram_boot_address = get_boot_address(args.ram_init)
soc_kwargs["integrated_main_ram_init"] = get_mem_data(args.ram_init,
data_width = bus_data_width,
endianness = cpu.endianness,
offset = ram_boot_offset
)
ram_boot_address = get_boot_address(args.ram_init)
elif args.with_sdram:
assert args.ram_init is None
soc_kwargs["sdram_module"] = args.sdram_module
@ -430,7 +438,11 @@ def main():
if args.sdram_from_spd_dump:
soc_kwargs["sdram_spd_data"] = parse_spd_hexdump(args.sdram_from_spd_dump)
if args.sdram_init is not None:
soc_kwargs["sdram_init"] = get_mem_data(args.sdram_init, endianness=cpu.endianness, offset=ram_boot_offset)
soc_kwargs["sdram_init"] = get_mem_data(args.sdram_init,
data_width = bus_data_width,
endianness = cpu.endianness,
offset = ram_boot_offset
)
ram_boot_address = get_boot_address(args.sdram_init)
# Ethernet.