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update de0nano example/ remove de1 (wip)

This commit is contained in:
Florent Kermarrec 2013-03-18 23:03:52 +01:00
parent 36f3556028
commit 24211574ec
12 changed files with 54 additions and 677 deletions
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8
examples/de0_nano/Makefile
View File

@ -1,13 +1,11 @@
PYTHON=C:\Python32\python
all: build/top.sta
build/top.sta:
cp top.sdc build/top.sdc
$(PYTHON) build.py
./build.py
load:
cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
cd build && quartus_pgm -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
clean:
rm -rf build/*

12
examples/de0_nano/build.py
View File

@ -1,3 +1,6 @@
#!/usr/bin/env python3
import os
from mibuild.platforms import de0nano
import top
@ -6,19 +9,14 @@ def main():
soc = top.SoC()
# set pin constraints
plat.request("led", obj=soc.led)
plat.request("gpio_2", obj=soc.gpio_2)
plat.request("led", 0, obj=soc.led)
plat.request("serial", 0, obj=soc.uart2csr)
# set extra constraints
plat.add_platform_command("""
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY "top"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
""")
plat.build_cmdline(soc.get_fragment())

174
examples/de0_nano/top.py
View File

@ -5,197 +5,53 @@
# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
# |___| |___| |___|
#
# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
# Copyright 2013 / Florent Kermarrec / florent@enjoy-digital.fr
#
# miscope example on De0 Nano Board
# ----------------------------------
# miscope example on De0 Nano
# ---------------------------
################################################################################
#
# In this example signals are generated in the FPGA.
# We use miscope to record those signals and visualize them.
#
# Example architecture:
# ----------------------
# miscope Config --> Python Client (Host) --> Vcd Output
# & Trig |
# Arduino (Uart<-->Spi Bridge)
# |
# De0 Nano
# |
# +--------------------+-----------------------+
# miIo Signal Generator miLa
# Control of Signal Ramp, Sinus, Logic Analyzer
# generator Square, ...
###############################################################################
#==============================================================================
# I M P O R T
#==============================================================================
from migen.fhdl.structure import *
from migen.fhdl.specials import Memory
from migen.fhdl import verilog, autofragment
from migen.fhdl.module import *
from migen.bus import csr
from migen.bus.transactions import *
from migen.bank import description, csrgen
from migen.bank.description import *
from miscope import trigger, recorder, miio, mila
from miscope.bridges import spi2csr
from miscope import miio
from miscope.bridges import uart2csr
from timings import *
from math import sin
#==============================================================================
# P A R A M E T E R S
#==============================================================================
#Timings Param
clk_freq = 50*MHz
clk_period_ns = clk_freq*ns
n = t2n(clk_period_ns)
# Bus Width
trig0_width = 16
dat0_width = 16
trig1_width = 32
dat1_width = 32
# Record Size
record_size = 4096
# Csr Addr
MIIO0_ADDR = 0x0000
MILA0_ADDR = 0x0200
MILA1_ADDR = 0x0600
#==============================================================================
# M I S C O P E E X A M P L E
#==============================================================================
class SoC:
class SoC(Module):
def __init__(self):
# migIo0
self.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
self.submodules.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
# migLa0
self.term0 = trigger.Term(trig0_width)
self.trigger0 = trigger.Trigger(trig0_width, [self.term0])
self.recorder0 = recorder.Recorder(dat0_width, record_size)
self.miLa0 = mila.MiLa(MILA0_ADDR, self.trigger0, self.recorder0)
# migLa1
self.term1 = trigger.Term(trig1_width)
self.trigger1 = trigger.Trigger(trig1_width, [self.term1])
self.recorder1 = recorder.Recorder(dat1_width, record_size)
self.miLa1 = mila.MiLa(MILA1_ADDR, self.trigger1, self.recorder1)
# Spi2Csr
self.spi2csr0 = spi2csr.Spi2Csr(16,8)
# Uart2Csr
self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
# Csr Interconnect
self.csrcon0 = csr.Interconnect(self.spi2csr0.csr,
self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr,
[
self.miIo0.bank.bus,
self.miLa0.trigger.bank.bus,
self.miLa0.recorder.bank.bus,
self.miLa1.trigger.bank.bus,
self.miLa1.recorder.bank.bus
self.miIo0.bank.bus
])
self.led = Signal()
self.clk50 = Signal()
self.led = Signal(8)
self.gpio_2 = Signal(13)
self.key = Signal(2)
self.cd_sys = ClockDomain("sys")
def get_fragment(self):
comb = []
sync = []
#
# Signal Generator
#
# Counter
cnt_gen = Signal(8)
sync += [
cnt_gen.eq(cnt_gen+1)
]
# Square
square_gen = Signal(8)
sync += [
If(cnt_gen[7],
square_gen.eq(255)
).Else(
square_gen.eq(0)
)
]
sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
sinus_re = Signal()
sinus_gen = Signal(8)
comb +=[sinus_re.eq(1)]
sinus_mem = Memory(8, 256, init = sinus)
sinus_port = sinus_mem.get_port(has_re=True)
comb += [
sinus_port.adr.eq(cnt_gen),
sinus_port.re.eq(sinus_re),
sinus_gen.eq(sinus_port.dat_r)
]
# Signal Selection
sig_gen = Signal(8)
comb += [
If(self.miIo0.o == 0,
sig_gen.eq(cnt_gen)
).Elif(self.miIo0.o == 1,
sig_gen.eq(square_gen)
).Elif(self.miIo0.o == 2,
sig_gen.eq(sinus_gen)
).Else(
sig_gen.eq(0)
)
]
###
# Led
comb += [self.led.eq(self.miIo0.o[:8])]
# MigLa0 input
comb += [
self.miLa0.trig.eq(sig_gen),
self.miLa0.dat.eq(sig_gen)
]
# MigLa1 input
comb += [
self.miLa1.trig[:8].eq(self.spi2csr0.csr.dat_w),
self.miLa1.trig[8:24].eq(self.spi2csr0.csr.adr),
self.miLa1.trig[24].eq(self.spi2csr0.csr.we),
self.miLa1.dat[:8].eq(self.spi2csr0.csr.dat_w),
self.miLa1.dat[8:24].eq(self.spi2csr0.csr.adr),
self.miLa1.dat[24].eq(self.spi2csr0.csr.we)
]
# Spi2Csr
self.spi2csr0.spi_clk = self.gpio_2[0]
self.spi2csr0.spi_cs_n = self.gpio_2[1]
self.spi2csr0.spi_mosi = self.gpio_2[2]
self.spi2csr0.spi_miso = self.gpio_2[3]
#
# Clocking / Reset
#
comb += [
self.cd_sys.clk.eq(self.clk50),
self.cd_sys.rst.eq(~self.key[0])
]
frag = autofragment.from_attributes(self)
frag += Fragment(comb, sync)
return frag
self.comb += self.led.eq(self.miIo0.o[0])

15
examples/de1/Makefile
View File

@ -1,15 +0,0 @@
PYTHON=C:\Python32\python
all: build/top.sta
build/top.sta:
cp top.sdc build/top.sdc
$(PYTHON) build.py
load:
cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
clean:
rm -rf build/*
.PHONY: load clean

34
examples/de1/build.py
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@ -1,34 +0,0 @@
import os
from mibuild.platforms import de1
from mibuild.altera_quartus import _add_period_constraint
import top
def main():
plat = de1.Platform()
soc = top.SoC()
# set pin constraints
plat.request("clk50", obj=soc.clk50)
plat.request("key", obj=soc.key)
plat.request("ledg", obj=soc.led)
plat.request("gpio_0", obj=soc.gpio_0)
# set extra constraints
plat.add_platform_command("""
set_global_assignment -name FAMILY "Cyclone IV E"
set_global_assignment -name TOP_LEVEL_ENTITY "top"
set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
""")
_add_period_constraint(plat, "sys_clk", 20.0)
cd = dict()
cd["sys"] = soc.cd_sys
plat.build_cmdline(soc.get_fragment(), clock_domains=cd)
if __name__ == "__main__":
main()

58
examples/de1/client/test_MiIo.py
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@ -1,58 +0,0 @@
from miscope import trigger, recorder, miIo
from miscope.bridges.spi2csr.tools.uart2Spi import *
#==============================================================================
# P A R A M E T E R S
#==============================================================================
# Bus Width
trig_width = 16
dat_width = 16
# Record Size
record_size = 1024
csr = Uart2Spi(1,115200)
# Csr Addr
MIIO_ADDR = 0x0000
# Miscope Configuration
# miIo
miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr)
def led_anim0():
for i in range(10):
miIo0.write(0xA5)
time.sleep(0.1)
miIo0.write(0x5A)
time.sleep(0.1)
def led_anim1():
#Led <<
for j in range(4):
ledData = 1
for i in range(8):
miIo0.write(ledData)
time.sleep(i*i*0.0020)
ledData = (ledData<<1)
#Led >>
ledData = 128
for i in range(8):
miIo0.write(ledData)
time.sleep(i*i*0.0020)
ledData = (ledData>>1)
#==============================================================================
# T E S T M I G I O
#==============================================================================
print("- Small Led Animation...")
led_anim0()
time.sleep(1)
led_anim1()
time.sleep(1)
print("- Read Switch: ",end=' ')
print(miIo0.read())

79
examples/de1/client/test_MiLa_0.py
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@ -1,79 +0,0 @@
from miscope import trigger, recorder, miIo, miLa
from miscope.tools.truthtable import *
from miscope.tools.vcd import *
from miscope.bridges.spi2csr.tools.uart2Spi import *
#==============================================================================
# P A R A M E T E R S
#==============================================================================
# Bus Width
trig_width = 16
dat_width = 16
# Record Size
record_size = 4096
# Csr Addr
MIIO_ADDR = 0x0000
MILA_ADDR = 0x0200
csr = Uart2Spi(1, 115200, debug=False)
# MiScope Configuration
# miIo0
miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr)
# miLa0
term0 = trigger.Term(trig_width)
trigger0 = trigger.Trigger(trig_width, [term0])
recorder0 = recorder.Recorder(dat_width, record_size)
miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr)
#==============================================================================
# T E S T M I G L A
#==============================================================================
dat_vcd = []
recorder0.size(1024)
def capture(size):
global trigger0
global recorder0
global dat_vcd
sum_tt = gen_truth_table("term0")
miLa0.trig.sum.write(sum_tt)
miLa0.rec.reset()
miLa0.rec.offset(0)
miLa0.rec.arm()
print("-Recorder [Armed]")
print("-Waiting Trigger...", end = ' ')
while(not miLa0.rec.is_done()):
time.sleep(0.1)
print("[Done]")
print("-Receiving Data...", end = ' ')
sys.stdout.flush()
dat_vcd += miLa0.rec.read(size)
print("[Done]")
print("Capturing Ramp..")
print("----------------------")
term0.write(0x0000,0xFFFF)
csr.write(0x0000, 0)
capture(1024)
print("Capturing Square..")
print("----------------------")
term0.write(0x0000,0xFFFF)
csr.write(0x0000, 1)
capture(1024)
print("Capturing Sinus..")
print("----------------------")
term0.write(0x0080,0xFFFF)
csr.write(0x0000, 2)
capture(1024)
myvcd = Vcd()
myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
myvcd.write("test_MiLa_0.vcd")

62
examples/de1/client/test_MiLa_1.py
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@ -1,62 +0,0 @@
from miscope import trigger, recorder, miIo, miLa
from miscope.tools.truthtable import *
from miscope.tools.vcd import *
from miscope.bridges.spi2csr.tools.uart2Spi import *
#==============================================================================
# P A R A M E T E R S
#==============================================================================
# Bus Width
trig_width = 32
dat_width = 32
# Record Size
record_size = 4096
# Csr Addr
MIIO0_ADDR = 0x0000
MILA1_ADDR = 0x0600
csr = Uart2Spi(1, 115200, debug=False)
# MiScope Configuration
# miIo0
miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr)
# miLa1
term1 = trigger.Term(trig_width)
trigger1 = trigger.Trigger(trig_width, [term1])
recorder1 = recorder.Recorder(dat_width, record_size)
miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr)
#==============================================================================
# T E S T M I G L A
#==============================================================================
dat_vcd = []
recorder1.size(1024)
term1.write(0x0100005A,0x0100005A)
sum_tt = gen_truth_table("term1")
miLa1.trig.sum.write(sum_tt)
miLa1.rec.reset()
miLa1.rec.offset(256)
miLa1.rec.arm()
print("-Recorder [Armed]")
print("-Waiting Trigger...", end = ' ')
csr.write(0x0000,0x5A)
while(not miLa1.rec.is_done()):
time.sleep(0.1)
print("[Done]")
print("-Receiving Data...", end = ' ')
sys.stdout.flush()
dat_vcd += miLa1.rec.read(1024)
print("[Done]")
myvcd = Vcd()
myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8)))
myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24)))
myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24)))
myvcd.write("test_MiLa_1.vcd")

29
examples/de1/timings.py
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@ -1,29 +0,0 @@
from math import ceil
Hz = 1
KHz = 10**3
MHz = 10**6
GHz = 10**9
s = 1
ms = 1/KHz
us = 1/MHz
ns = 1/GHz
class t2n:
def __init__(self, clk_period_ns):
self.clk_period_ns = clk_period_ns
self.clk_period_us = clk_period_ns*(MHz/GHz)
self.clk_period_ms = clk_period_ns*(KHz/GHz)
def ns(self,t,margin=True):
if margin:
t += self.clk_period_ns/2
return ceil(t/self.clk_period_ns)
def us(self,t,margin=True):
if margin:
t += self.clk_period_us/2
return ceil(t/self.clk_period_us)
def ms(self,t,margin=True):
if margin:
t += self.clk_period_ms/2
return ceil(t/self.clk_period_ms)

201
examples/de1/top.py
View File

@ -1,201 +0,0 @@
################################################################################
# _____ _ ____ _ _ _ _
# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
# | __| | | | . | | | | | | | . | | _| .'| |
# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
# |___| |___| |___|
#
# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
#
# miscope Example on De1 Board
# ----------------------------------
################################################################################
#
# In this example signals are generated in the FPGA.
# We use miscope to record those signals and visualize them.
#
# Example architecture:
# ----------------------
# miscope Config --> Python Client (Host) --> Vcd Output
# & Trig |
# Arduino (Uart<-->Spi Bridge)
# |
# De1
# |
# +--------------------+-----------------------+
# miIo Signal Generator miLa
# Control of Signal Ramp, Sinus, Logic Analyzer
# generator Square, ...
###############################################################################
#==============================================================================
# I M P O R T
#==============================================================================
from migen.fhdl.structure import *
from migen.fhdl.specials import Memory
from migen.fhdl import verilog, autofragment
from migen.bus import csr
from migen.bus.transactions import *
from migen.bank import description, csrgen
from migen.bank.description import *
from miscope import trigger, recorder, miio, mila
from miscope.bridges import spi2csr
from timings import *
from math import sin
#==============================================================================
# P A R A M E T E R S
#==============================================================================
#Timings Param
clk_freq = 50*MHz
clk_period_ns = clk_freq*ns
n = t2n(clk_period_ns)
# Bus Width
trig0_width = 16
dat0_width = 16
trig1_width = 32
dat1_width = 32
# Record Size
record_size = 4096
# Csr Addr
MIIO0_ADDR = 0x0000
MILA0_ADDR = 0x0200
MILA1_ADDR = 0x0600
#==============================================================================
# M I S C O P E E X A M P L E
#==============================================================================
class SoC:
def __init__(self):
# migIo0
self.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
# migLa0
self.term0 = trigger.Term(trig0_width)
self.trigger0 = trigger.Trigger(trig0_width, [self.term0])
self.recorder0 = recorder.Recorder(dat0_width, record_size)
self.miLa0 = mila.MiLa(MILA0_ADDR, self.trigger0, self.recorder0)
# migLa1
self.term1 = trigger.Term(trig1_width)
self.trigger1 = trigger.Trigger(trig1_width, [self.term1])
self.recorder1 = recorder.Recorder(dat1_width, record_size)
self.miLa1 = mila.MiLa(MILA1_ADDR, self.trigger1, self.recorder1)
# Spi2Csr
self.spi2csr0 = spi2csr.Spi2Csr(16,8)
# Csr Interconnect
self.csrcon0 = csr.Interconnect(self.spi2csr0.csr,
[
self.miIo0.bank.bus,
self.miLa0.trigger.bank.bus,
self.miLa0.recorder.bank.bus,
self.miLa1.trigger.bank.bus,
self.miLa1.recorder.bank.bus
])
self.clk50 = Signal()
self.led = Signal(8)
self.gpio_0 = Signal(36)
self.key = Signal(4)
self.cd_sys = ClockDomain("sys")
def get_fragment(self):
comb = []
sync = []
#
# Signal Generator
#
# Counter
cnt_gen = Signal(8)
sync += [
cnt_gen.eq(cnt_gen+1)
]
# Square
square_gen = Signal(8)
sync += [
If(cnt_gen[7],
square_gen.eq(255)
).Else(
square_gen.eq(0)
)
]
sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
sinus_re = Signal()
sinus_gen = Signal(8)
comb +=[sinus_re.eq(1)]
sinus_mem = Memory(8, 256, init = sinus)
sinus_port = sinus_mem.get_port(has_re=True)
comb += [
sinus_port.adr.eq(cnt_gen),
sinus_port.re.eq(sinus_re),
sinus_gen.eq(sinus_port.dat_r)
]
# Signal Selection
sig_gen = Signal(8)
comb += [
If(self.miIo0.o == 0,
sig_gen.eq(cnt_gen)
).Elif(self.miIo0.o == 1,
sig_gen.eq(square_gen)
).Elif(self.miIo0.o == 2,
sig_gen.eq(sinus_gen)
).Else(
sig_gen.eq(0)
)
]
# Led
comb += [self.led.eq(self.miIo0.o[:8])]
# MigLa0 input
comb += [
self.miLa0.trig.eq(sig_gen),
self.miLa0.dat.eq(sig_gen)
]
# MigLa1 input
comb += [
self.miLa1.trig[:8].eq(self.spi2csr0.csr.dat_w),
self.miLa1.trig[8:24].eq(self.spi2csr0.csr.adr),
self.miLa1.trig[24].eq(self.spi2csr0.csr.we),
self.miLa1.dat[:8].eq(self.spi2csr0.csr.dat_w),
self.miLa1.dat[8:24].eq(self.spi2csr0.csr.adr),
self.miLa1.dat[24].eq(self.spi2csr0.csr.we)
]
# Spi2Csr
self.spi2csr0.spi_clk = self.gpio_0[0]
self.spi2csr0.spi_cs_n = self.gpio_0[1]
self.spi2csr0.spi_mosi = self.gpio_0[2]
self.spi2csr0.spi_miso = self.gpio_0[3]
#
# Clocking / Reset
#
comb += [
self.cd_sys.clk.eq(self.clk50),
self.cd_sys.rst.eq(~self.key[0])
]
frag = autofragment.from_attributes(self)
frag += Fragment(comb, sync)
return frag

49
miscope/bridges/uart2csr/__init__.py
View File

@ -1,7 +1,7 @@
from migen.fhdl.structure import *
from migen.genlib.misc import *
from migen.genlib.cdc import *
from migen.fhdl.module import *
from migen.bus import csr
from migen.genlib.fsm import *
from miscope.bridges.uart2csr.uart import *
@ -20,8 +20,8 @@ class Uart2Csr(Module):
###
uart = Uart(clk_freq, baud)
self.specials +=uart
self.submodules.uart = UART(clk_freq, baud)
uart = self.uart
#
# In/Out
@ -38,21 +38,24 @@ class Uart2Csr(Module):
addr = Signal(32)
data = Signal(8)
# FSM
self.submodules.fsm = FSM("IDLE",
"GET_BL", "GET_ADDR",
"GET_DATA", "WRITE_CSR",
"READ_CSR", "SEND_DATA")
fsm = self.fsm
#
# Global
#
self.sync +=[
If(fsm.ongoing(fsm.IDLE), cnt.eq(0)
).Elif(uart_rx_ev, cnt.eq(cnt + 1)),
).Elif(uart.rx_ev, cnt.eq(cnt + 1)),
sr.eq(Cat(uart.rx_dat, sr[0:24]))
]
# FSM
fsm = FSM("IDLE",
"GET_BL", "GET_ADDR",
"GET_DATA", "WRITE_CSR",
"READ_CSR", "SEND_DATA")
# State done
get_bl_done = Signal()
@ -64,13 +67,13 @@ class Uart2Csr(Module):
# Idle
#
fsm.act(fsm.IDLE,
If(uart.rx_ev and (uart.rx_dat == WRITE_CMD or uart.rx_dat == READ_CMD),
If(uart.rx_ev & ((uart.rx_dat == WRITE_CMD) | (uart.rx_dat == READ_CMD)),
fsm.next_state(fsm.GET_BL)
)
)
self.sync +=[
If(fsm.ongoing(fsm.IDLE) and uart_rx_env,
If(fsm.ongoing(fsm.IDLE) & uart.rx_ev,
cmd.eq(uart.rx_dat)
)
@ -85,7 +88,7 @@ class Uart2Csr(Module):
)
)
self.comb += get_bl_done.eq(uart_rx_ev and fsm.ongoing(fsm.GET_BL))
self.comb += get_bl_done.eq(uart.rx_ev & fsm.ongoing(fsm.GET_BL))
self.sync +=[
If(get_bl_done,
@ -97,19 +100,19 @@ class Uart2Csr(Module):
# Get address
#
fsm.act(fsm.GET_ADDR,
If(get_addr_done and cmd == WRITE_CMD,
If(get_addr_done & (cmd == WRITE_CMD),
fsm.next_state(fsm.GET_DATA)
).Elif(get_addr_done and cmd == READ_CMD,
).Elif(get_addr_done & (cmd == READ_CMD),
fsm.next_state(fsm.READ_CSR)
)
)
self.comb += get_addr_done.eq(uart_rx_ev and rx_cnt == 4 and fsm.ongoing(fsm.GET_ADDR))
self.comb += get_addr_done.eq(uart.rx_ev & (cnt == 4) & fsm.ongoing(fsm.GET_ADDR))
self.sync +=[
If(get_addr_done,
addr.eq(sr)
).Elif(write_data_done or send_data_done,
).Elif(get_data_done | send_data_done,
addr.eq(addr + 4)
)
]
@ -123,7 +126,7 @@ class Uart2Csr(Module):
)
)
self.comb += get_data_done.eq(uart_rx_ev and fsm.ongoing(fsm.GET_DATA))
self.comb += get_data_done.eq(uart.rx_ev & fsm.ongoing(fsm.GET_DATA))
self.sync +=[
If(get_data_done,
@ -152,7 +155,7 @@ class Uart2Csr(Module):
# Send Data
#
fsm.act(fsm.SEND_DATA,
If(send_data_done and (not burst_cnt),
If(send_data_done & (not burst_cnt),
fsm.next_state(fsm.IDLE)
).Elif(send_data_done,
fsm.next_state(fsm.READ_CSR)
@ -160,9 +163,9 @@ class Uart2Csr(Module):
)
self.comb += [
uart.tx_dat.eq(csr.dat_r),
uart.we.eq(fsm.entering(fsm.SEND_DATA)),
send_data_done.eq(~uart.we or uart.tx_ev)
uart.tx_dat.eq(self.csr.dat_r),
uart.tx_we.eq(fsm.entering(fsm.SEND_DATA)),
send_data_done.eq(~uart.tx_we | uart.tx_ev)
]
#
@ -171,7 +174,7 @@ class Uart2Csr(Module):
self.sync +=[
self.csr.adr.eq(addr),
self.csr.dat_w.eq(data),
If(fsm.ongoing(fsm.WRITE_CSR,
If(fsm.ongoing(fsm.WRITE_CSR),
self.csr.we.eq(1)
).Else(
self.csr.we.eq(0)

4
miscope/miio.py
View File

@ -28,10 +28,10 @@ class MiIo:
comb = []
if "I" in self.mode:
comb += self.ireg.field.w.eq(self.i)
comb += [self.ireg.field.w.eq(self.i)]
if "O" in self.mode:
comb += self.o.eq(self.oreg.field.r)
comb += [self.o.eq(self.oreg.field.r)]
return Fragment(comb) + self.bank.get_fragment()
#