update de0nano example/ remove de1 (wip)
This commit is contained in:
Florent Kermarrec
parent
36f3556028
commit
24211574ec
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@ -1,13 +1,11 @@
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PYTHON=C:\Python32\python
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all: build/top.sta
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build/top.sta:
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cp top.sdc build/top.sdc
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$(PYTHON) build.py
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./build.py
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load:
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cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
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cd build && quartus_pgm -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
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clean:
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rm -rf build/*
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@ -1,3 +1,6 @@
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#!/usr/bin/env python3
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import os
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from mibuild.platforms import de0nano
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import top
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@ -6,19 +9,14 @@ def main():
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soc = top.SoC()
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# set pin constraints
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plat.request("led", obj=soc.led)
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plat.request("gpio_2", obj=soc.gpio_2)
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plat.request("led", 0, obj=soc.led)
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plat.request("serial", 0, obj=soc.uart2csr)
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# set extra constraints
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plat.add_platform_command("""
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name TOP_LEVEL_ENTITY "top"
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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""")
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plat.build_cmdline(soc.get_fragment())
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@ -5,197 +5,53 @@
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# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
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# |___| |___| |___|
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#
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# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
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# Copyright 2013 / Florent Kermarrec / florent@enjoy-digital.fr
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#
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# miscope example on De0 Nano Board
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# ----------------------------------
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# miscope example on De0 Nano
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# ---------------------------
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################################################################################
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#
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# In this example signals are generated in the FPGA.
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# We use miscope to record those signals and visualize them.
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#
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# Example architecture:
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# ----------------------
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# miscope Config --> Python Client (Host) --> Vcd Output
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# & Trig |
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# Arduino (Uart<-->Spi Bridge)
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# |
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# De0 Nano
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# |
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# +--------------------+-----------------------+
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# miIo Signal Generator miLa
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# Control of Signal Ramp, Sinus, Logic Analyzer
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# generator Square, ...
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###############################################################################
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#==============================================================================
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# I M P O R T
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#==============================================================================
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from migen.fhdl.structure import *
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from migen.fhdl.specials import Memory
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from migen.fhdl import verilog, autofragment
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from migen.fhdl.module import *
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from migen.bus import csr
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from migen.bus.transactions import *
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from migen.bank import description, csrgen
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from migen.bank.description import *
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from miscope import trigger, recorder, miio, mila
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from miscope.bridges import spi2csr
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from miscope import miio
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from miscope.bridges import uart2csr
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from timings import *
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from math import sin
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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#Timings Param
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clk_freq = 50*MHz
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clk_period_ns = clk_freq*ns
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n = t2n(clk_period_ns)
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# Bus Width
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trig0_width = 16
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dat0_width = 16
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trig1_width = 32
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dat1_width = 32
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# Record Size
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record_size = 4096
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# Csr Addr
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MIIO0_ADDR = 0x0000
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MILA0_ADDR = 0x0200
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MILA1_ADDR = 0x0600
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#==============================================================================
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# M I S C O P E E X A M P L E
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# M I S C O P E E X A M P L E
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#==============================================================================
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class SoC:
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class SoC(Module):
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def __init__(self):
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# migIo0
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self.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
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self.submodules.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
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# migLa0
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self.term0 = trigger.Term(trig0_width)
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self.trigger0 = trigger.Trigger(trig0_width, [self.term0])
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self.recorder0 = recorder.Recorder(dat0_width, record_size)
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self.miLa0 = mila.MiLa(MILA0_ADDR, self.trigger0, self.recorder0)
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# migLa1
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self.term1 = trigger.Term(trig1_width)
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self.trigger1 = trigger.Trigger(trig1_width, [self.term1])
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self.recorder1 = recorder.Recorder(dat1_width, record_size)
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self.miLa1 = mila.MiLa(MILA1_ADDR, self.trigger1, self.recorder1)
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# Spi2Csr
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self.spi2csr0 = spi2csr.Spi2Csr(16,8)
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# Uart2Csr
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self.submodules.uart2csr = uart2csr.Uart2Csr(clk_freq, 115200)
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# Csr Interconnect
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self.csrcon0 = csr.Interconnect(self.spi2csr0.csr,
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self.submodules.csrcon = csr.Interconnect(self.uart2csr.csr,
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[
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self.miIo0.bank.bus,
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self.miLa0.trigger.bank.bus,
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self.miLa0.recorder.bank.bus,
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self.miLa1.trigger.bank.bus,
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self.miLa1.recorder.bank.bus
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self.miIo0.bank.bus
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])
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self.led = Signal()
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self.clk50 = Signal()
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self.led = Signal(8)
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self.gpio_2 = Signal(13)
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self.key = Signal(2)
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self.cd_sys = ClockDomain("sys")
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def get_fragment(self):
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comb = []
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sync = []
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#
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# Signal Generator
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#
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# Counter
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cnt_gen = Signal(8)
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sync += [
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cnt_gen.eq(cnt_gen+1)
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]
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# Square
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square_gen = Signal(8)
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sync += [
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If(cnt_gen[7],
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square_gen.eq(255)
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).Else(
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square_gen.eq(0)
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)
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]
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sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
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sinus_re = Signal()
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sinus_gen = Signal(8)
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comb +=[sinus_re.eq(1)]
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sinus_mem = Memory(8, 256, init = sinus)
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sinus_port = sinus_mem.get_port(has_re=True)
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comb += [
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sinus_port.adr.eq(cnt_gen),
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sinus_port.re.eq(sinus_re),
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sinus_gen.eq(sinus_port.dat_r)
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]
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# Signal Selection
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sig_gen = Signal(8)
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comb += [
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If(self.miIo0.o == 0,
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sig_gen.eq(cnt_gen)
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).Elif(self.miIo0.o == 1,
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sig_gen.eq(square_gen)
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).Elif(self.miIo0.o == 2,
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sig_gen.eq(sinus_gen)
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).Else(
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sig_gen.eq(0)
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)
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]
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###
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# Led
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comb += [self.led.eq(self.miIo0.o[:8])]
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# MigLa0 input
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comb += [
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self.miLa0.trig.eq(sig_gen),
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self.miLa0.dat.eq(sig_gen)
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]
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# MigLa1 input
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comb += [
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self.miLa1.trig[:8].eq(self.spi2csr0.csr.dat_w),
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self.miLa1.trig[8:24].eq(self.spi2csr0.csr.adr),
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self.miLa1.trig[24].eq(self.spi2csr0.csr.we),
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self.miLa1.dat[:8].eq(self.spi2csr0.csr.dat_w),
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self.miLa1.dat[8:24].eq(self.spi2csr0.csr.adr),
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self.miLa1.dat[24].eq(self.spi2csr0.csr.we)
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]
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# Spi2Csr
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self.spi2csr0.spi_clk = self.gpio_2[0]
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self.spi2csr0.spi_cs_n = self.gpio_2[1]
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self.spi2csr0.spi_mosi = self.gpio_2[2]
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self.spi2csr0.spi_miso = self.gpio_2[3]
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#
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# Clocking / Reset
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#
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comb += [
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self.cd_sys.clk.eq(self.clk50),
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self.cd_sys.rst.eq(~self.key[0])
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]
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frag = autofragment.from_attributes(self)
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frag += Fragment(comb, sync)
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return frag
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self.comb += self.led.eq(self.miIo0.o[0])
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@ -1,15 +0,0 @@
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PYTHON=C:\Python32\python
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all: build/top.sta
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build/top.sta:
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cp top.sdc build/top.sdc
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$(PYTHON) build.py
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load:
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cd build && quartus_pgm.exe -m jtag -c USB-Blaster[USB-0] -o "p;top.sof"
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clean:
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rm -rf build/*
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.PHONY: load clean
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@ -1,34 +0,0 @@
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import os
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from mibuild.platforms import de1
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from mibuild.altera_quartus import _add_period_constraint
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import top
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def main():
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plat = de1.Platform()
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soc = top.SoC()
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# set pin constraints
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plat.request("clk50", obj=soc.clk50)
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plat.request("key", obj=soc.key)
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plat.request("ledg", obj=soc.led)
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plat.request("gpio_0", obj=soc.gpio_0)
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# set extra constraints
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plat.add_platform_command("""
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set_global_assignment -name FAMILY "Cyclone IV E"
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set_global_assignment -name TOP_LEVEL_ENTITY "top"
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set_global_assignment -name VERILOG_INPUT_VERSION SYSTEMVERILOG_2005
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set_global_assignment -name CYCLONEII_RESERVE_NCEO_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_FLASH_NCE_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA0_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DATA1_AFTER_CONFIGURATION "USE AS REGULAR IO"
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set_global_assignment -name RESERVE_DCLK_AFTER_CONFIGURATION "USE AS REGULAR IO"
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""")
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_add_period_constraint(plat, "sys_clk", 20.0)
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cd = dict()
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cd["sys"] = soc.cd_sys
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plat.build_cmdline(soc.get_fragment(), clock_domains=cd)
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if __name__ == "__main__":
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main()
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@ -1,58 +0,0 @@
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from miscope import trigger, recorder, miIo
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from miscope.bridges.spi2csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 1024
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csr = Uart2Spi(1,115200)
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# Csr Addr
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MIIO_ADDR = 0x0000
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# Miscope Configuration
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# miIo
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miIo0 = miIo.MiIo(MIIO_ADDR, 8, "IO", csr)
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def led_anim0():
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for i in range(10):
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miIo0.write(0xA5)
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time.sleep(0.1)
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miIo0.write(0x5A)
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time.sleep(0.1)
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def led_anim1():
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#Led <<
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for j in range(4):
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ledData = 1
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for i in range(8):
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miIo0.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData<<1)
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#Led >>
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ledData = 128
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for i in range(8):
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miIo0.write(ledData)
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time.sleep(i*i*0.0020)
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ledData = (ledData>>1)
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#==============================================================================
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# T E S T M I G I O
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#==============================================================================
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print("- Small Led Animation...")
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led_anim0()
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time.sleep(1)
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led_anim1()
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time.sleep(1)
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print("- Read Switch: ",end=' ')
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print(miIo0.read())
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@ -1,79 +0,0 @@
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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from miscope.bridges.spi2csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 16
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dat_width = 16
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# Record Size
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record_size = 4096
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# Csr Addr
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MIIO_ADDR = 0x0000
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MILA_ADDR = 0x0200
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csr = Uart2Spi(1, 115200, debug=False)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO_ADDR, 8, "IO",csr)
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# miLa0
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term0 = trigger.Term(trig_width)
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trigger0 = trigger.Trigger(trig_width, [term0])
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recorder0 = recorder.Recorder(dat_width, record_size)
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miLa0 = miLa.MiLa(MILA_ADDR, trigger0, recorder0, csr)
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#==============================================================================
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# T E S T M I G L A
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#==============================================================================
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dat_vcd = []
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recorder0.size(1024)
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def capture(size):
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global trigger0
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global recorder0
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global dat_vcd
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sum_tt = gen_truth_table("term0")
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miLa0.trig.sum.write(sum_tt)
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miLa0.rec.reset()
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miLa0.rec.offset(0)
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miLa0.rec.arm()
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print("-Recorder [Armed]")
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print("-Waiting Trigger...", end = ' ')
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while(not miLa0.rec.is_done()):
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time.sleep(0.1)
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print("[Done]")
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print("-Receiving Data...", end = ' ')
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sys.stdout.flush()
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dat_vcd += miLa0.rec.read(size)
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print("[Done]")
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print("Capturing Ramp..")
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print("----------------------")
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term0.write(0x0000,0xFFFF)
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csr.write(0x0000, 0)
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capture(1024)
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print("Capturing Square..")
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print("----------------------")
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term0.write(0x0000,0xFFFF)
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csr.write(0x0000, 1)
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capture(1024)
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print("Capturing Sinus..")
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print("----------------------")
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term0.write(0x0080,0xFFFF)
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csr.write(0x0000, 2)
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capture(1024)
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myvcd = Vcd()
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myvcd.add(Var("wire", 16, "trig_dat", dat_vcd))
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myvcd.write("test_MiLa_0.vcd")
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@ -1,62 +0,0 @@
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from miscope import trigger, recorder, miIo, miLa
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from miscope.tools.truthtable import *
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from miscope.tools.vcd import *
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from miscope.bridges.spi2csr.tools.uart2Spi import *
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#==============================================================================
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# P A R A M E T E R S
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#==============================================================================
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# Bus Width
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trig_width = 32
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dat_width = 32
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# Record Size
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record_size = 4096
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# Csr Addr
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MIIO0_ADDR = 0x0000
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MILA1_ADDR = 0x0600
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csr = Uart2Spi(1, 115200, debug=False)
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# MiScope Configuration
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# miIo0
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miIo0 = miIo.MigIo(MIIO0_ADDR, 8, "IO",csr)
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# miLa1
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term1 = trigger.Term(trig_width)
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trigger1 = trigger.Trigger(trig_width, [term1])
|
||||
recorder1 = recorder.Recorder(dat_width, record_size)
|
||||
|
||||
miLa1 = miLa.MiLa(MILA1_ADDR, trigger1, recorder1, csr)
|
||||
|
||||
#==============================================================================
|
||||
# T E S T M I G L A
|
||||
#==============================================================================
|
||||
dat_vcd = []
|
||||
recorder1.size(1024)
|
||||
|
||||
term1.write(0x0100005A,0x0100005A)
|
||||
sum_tt = gen_truth_table("term1")
|
||||
miLa1.trig.sum.write(sum_tt)
|
||||
miLa1.rec.reset()
|
||||
miLa1.rec.offset(256)
|
||||
miLa1.rec.arm()
|
||||
|
||||
print("-Recorder [Armed]")
|
||||
print("-Waiting Trigger...", end = ' ')
|
||||
csr.write(0x0000,0x5A)
|
||||
while(not miLa1.rec.is_done()):
|
||||
time.sleep(0.1)
|
||||
print("[Done]")
|
||||
|
||||
print("-Receiving Data...", end = ' ')
|
||||
sys.stdout.flush()
|
||||
dat_vcd += miLa1.rec.read(1024)
|
||||
print("[Done]")
|
||||
|
||||
myvcd = Vcd()
|
||||
myvcd.add(Var("wire", 8, "csr_dat_w", get_bits(dat_vcd, 32, 0, 8)))
|
||||
myvcd.add(Var("wire", 16, "csr_adr", get_bits(dat_vcd, 32, 8, 24)))
|
||||
myvcd.add(Var("wire", 1, "csr_we", get_bits(dat_vcd, 32, 24)))
|
||||
myvcd.write("test_MiLa_1.vcd")
|
||||
|
|
@ -1,29 +0,0 @@
|
|||
from math import ceil
|
||||
|
||||
Hz = 1
|
||||
KHz = 10**3
|
||||
MHz = 10**6
|
||||
GHz = 10**9
|
||||
|
||||
s = 1
|
||||
ms = 1/KHz
|
||||
us = 1/MHz
|
||||
ns = 1/GHz
|
||||
|
||||
class t2n:
|
||||
def __init__(self, clk_period_ns):
|
||||
self.clk_period_ns = clk_period_ns
|
||||
self.clk_period_us = clk_period_ns*(MHz/GHz)
|
||||
self.clk_period_ms = clk_period_ns*(KHz/GHz)
|
||||
def ns(self,t,margin=True):
|
||||
if margin:
|
||||
t += self.clk_period_ns/2
|
||||
return ceil(t/self.clk_period_ns)
|
||||
def us(self,t,margin=True):
|
||||
if margin:
|
||||
t += self.clk_period_us/2
|
||||
return ceil(t/self.clk_period_us)
|
||||
def ms(self,t,margin=True):
|
||||
if margin:
|
||||
t += self.clk_period_ms/2
|
||||
return ceil(t/self.clk_period_ms)
|
||||
|
|
@ -1,201 +0,0 @@
|
|||
################################################################################
|
||||
# _____ _ ____ _ _ _ _
|
||||
# | __|___ |_|___ _ _ | \|_|___|_| |_ ___| |
|
||||
# | __| | | | . | | | | | | | . | | _| .'| |
|
||||
# |_____|_|_|_| |___|_ | |____/|_|_ |_|_| |__,|_|
|
||||
# |___| |___| |___|
|
||||
#
|
||||
# Copyright 2012 / Florent Kermarrec / florent@enjoy-digital.fr
|
||||
#
|
||||
# miscope Example on De1 Board
|
||||
# ----------------------------------
|
||||
################################################################################
|
||||
#
|
||||
# In this example signals are generated in the FPGA.
|
||||
# We use miscope to record those signals and visualize them.
|
||||
#
|
||||
# Example architecture:
|
||||
# ----------------------
|
||||
# miscope Config --> Python Client (Host) --> Vcd Output
|
||||
# & Trig |
|
||||
# Arduino (Uart<-->Spi Bridge)
|
||||
# |
|
||||
# De1
|
||||
# |
|
||||
# +--------------------+-----------------------+
|
||||
# miIo Signal Generator miLa
|
||||
# Control of Signal Ramp, Sinus, Logic Analyzer
|
||||
# generator Square, ...
|
||||
###############################################################################
|
||||
|
||||
|
||||
#==============================================================================
|
||||
# I M P O R T
|
||||
#==============================================================================
|
||||
from migen.fhdl.structure import *
|
||||
from migen.fhdl.specials import Memory
|
||||
from migen.fhdl import verilog, autofragment
|
||||
from migen.bus import csr
|
||||
from migen.bus.transactions import *
|
||||
from migen.bank import description, csrgen
|
||||
from migen.bank.description import *
|
||||
|
||||
from miscope import trigger, recorder, miio, mila
|
||||
from miscope.bridges import spi2csr
|
||||
|
||||
from timings import *
|
||||
|
||||
from math import sin
|
||||
|
||||
#==============================================================================
|
||||
# P A R A M E T E R S
|
||||
#==============================================================================
|
||||
|
||||
#Timings Param
|
||||
clk_freq = 50*MHz
|
||||
clk_period_ns = clk_freq*ns
|
||||
n = t2n(clk_period_ns)
|
||||
|
||||
# Bus Width
|
||||
trig0_width = 16
|
||||
dat0_width = 16
|
||||
|
||||
trig1_width = 32
|
||||
dat1_width = 32
|
||||
|
||||
# Record Size
|
||||
record_size = 4096
|
||||
|
||||
# Csr Addr
|
||||
MIIO0_ADDR = 0x0000
|
||||
MILA0_ADDR = 0x0200
|
||||
MILA1_ADDR = 0x0600
|
||||
|
||||
#==============================================================================
|
||||
# M I S C O P E E X A M P L E
|
||||
#==============================================================================
|
||||
class SoC:
|
||||
def __init__(self):
|
||||
# migIo0
|
||||
self.miIo0 = miio.MiIo(MIIO0_ADDR, 8, "IO")
|
||||
|
||||
# migLa0
|
||||
self.term0 = trigger.Term(trig0_width)
|
||||
self.trigger0 = trigger.Trigger(trig0_width, [self.term0])
|
||||
self.recorder0 = recorder.Recorder(dat0_width, record_size)
|
||||
|
||||
self.miLa0 = mila.MiLa(MILA0_ADDR, self.trigger0, self.recorder0)
|
||||
|
||||
# migLa1
|
||||
self.term1 = trigger.Term(trig1_width)
|
||||
self.trigger1 = trigger.Trigger(trig1_width, [self.term1])
|
||||
self.recorder1 = recorder.Recorder(dat1_width, record_size)
|
||||
|
||||
self.miLa1 = mila.MiLa(MILA1_ADDR, self.trigger1, self.recorder1)
|
||||
|
||||
# Spi2Csr
|
||||
self.spi2csr0 = spi2csr.Spi2Csr(16,8)
|
||||
|
||||
# Csr Interconnect
|
||||
self.csrcon0 = csr.Interconnect(self.spi2csr0.csr,
|
||||
[
|
||||
self.miIo0.bank.bus,
|
||||
self.miLa0.trigger.bank.bus,
|
||||
self.miLa0.recorder.bank.bus,
|
||||
self.miLa1.trigger.bank.bus,
|
||||
self.miLa1.recorder.bank.bus
|
||||
])
|
||||
|
||||
self.clk50 = Signal()
|
||||
self.led = Signal(8)
|
||||
self.gpio_0 = Signal(36)
|
||||
self.key = Signal(4)
|
||||
self.cd_sys = ClockDomain("sys")
|
||||
|
||||
def get_fragment(self):
|
||||
comb = []
|
||||
sync = []
|
||||
|
||||
#
|
||||
# Signal Generator
|
||||
#
|
||||
|
||||
# Counter
|
||||
cnt_gen = Signal(8)
|
||||
sync += [
|
||||
cnt_gen.eq(cnt_gen+1)
|
||||
]
|
||||
|
||||
# Square
|
||||
square_gen = Signal(8)
|
||||
sync += [
|
||||
If(cnt_gen[7],
|
||||
square_gen.eq(255)
|
||||
).Else(
|
||||
square_gen.eq(0)
|
||||
)
|
||||
]
|
||||
|
||||
sinus = [int(128*sin((2*3.1415)/256*(x+1)))+128 for x in range(256)]
|
||||
sinus_re = Signal()
|
||||
sinus_gen = Signal(8)
|
||||
comb +=[sinus_re.eq(1)]
|
||||
sinus_mem = Memory(8, 256, init = sinus)
|
||||
sinus_port = sinus_mem.get_port(has_re=True)
|
||||
comb += [
|
||||
sinus_port.adr.eq(cnt_gen),
|
||||
sinus_port.re.eq(sinus_re),
|
||||
sinus_gen.eq(sinus_port.dat_r)
|
||||
]
|
||||
|
||||
# Signal Selection
|
||||
sig_gen = Signal(8)
|
||||
comb += [
|
||||
If(self.miIo0.o == 0,
|
||||
sig_gen.eq(cnt_gen)
|
||||
).Elif(self.miIo0.o == 1,
|
||||
sig_gen.eq(square_gen)
|
||||
).Elif(self.miIo0.o == 2,
|
||||
sig_gen.eq(sinus_gen)
|
||||
).Else(
|
||||
sig_gen.eq(0)
|
||||
)
|
||||
]
|
||||
|
||||
# Led
|
||||
comb += [self.led.eq(self.miIo0.o[:8])]
|
||||
|
||||
|
||||
# MigLa0 input
|
||||
comb += [
|
||||
self.miLa0.trig.eq(sig_gen),
|
||||
self.miLa0.dat.eq(sig_gen)
|
||||
]
|
||||
|
||||
# MigLa1 input
|
||||
comb += [
|
||||
self.miLa1.trig[:8].eq(self.spi2csr0.csr.dat_w),
|
||||
self.miLa1.trig[8:24].eq(self.spi2csr0.csr.adr),
|
||||
self.miLa1.trig[24].eq(self.spi2csr0.csr.we),
|
||||
self.miLa1.dat[:8].eq(self.spi2csr0.csr.dat_w),
|
||||
self.miLa1.dat[8:24].eq(self.spi2csr0.csr.adr),
|
||||
self.miLa1.dat[24].eq(self.spi2csr0.csr.we)
|
||||
]
|
||||
|
||||
# Spi2Csr
|
||||
self.spi2csr0.spi_clk = self.gpio_0[0]
|
||||
self.spi2csr0.spi_cs_n = self.gpio_0[1]
|
||||
self.spi2csr0.spi_mosi = self.gpio_0[2]
|
||||
self.spi2csr0.spi_miso = self.gpio_0[3]
|
||||
|
||||
#
|
||||
# Clocking / Reset
|
||||
#
|
||||
comb += [
|
||||
self.cd_sys.clk.eq(self.clk50),
|
||||
self.cd_sys.rst.eq(~self.key[0])
|
||||
]
|
||||
|
||||
frag = autofragment.from_attributes(self)
|
||||
frag += Fragment(comb, sync)
|
||||
return frag
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
from migen.fhdl.structure import *
|
||||
from migen.genlib.misc import *
|
||||
from migen.genlib.cdc import *
|
||||
from migen.fhdl.module import *
|
||||
from migen.bus import csr
|
||||
from migen.genlib.fsm import *
|
||||
|
||||
from miscope.bridges.uart2csr.uart import *
|
||||
|
||||
|
|
@ -20,8 +20,8 @@ class Uart2Csr(Module):
|
|||
|
||||
###
|
||||
|
||||
uart = Uart(clk_freq, baud)
|
||||
self.specials +=uart
|
||||
self.submodules.uart = UART(clk_freq, baud)
|
||||
uart = self.uart
|
||||
|
||||
#
|
||||
# In/Out
|
||||
|
|
@ -38,21 +38,24 @@ class Uart2Csr(Module):
|
|||
addr = Signal(32)
|
||||
data = Signal(8)
|
||||
|
||||
|
||||
# FSM
|
||||
self.submodules.fsm = FSM("IDLE",
|
||||
"GET_BL", "GET_ADDR",
|
||||
"GET_DATA", "WRITE_CSR",
|
||||
"READ_CSR", "SEND_DATA")
|
||||
|
||||
fsm = self.fsm
|
||||
#
|
||||
# Global
|
||||
#
|
||||
self.sync +=[
|
||||
If(fsm.ongoing(fsm.IDLE), cnt.eq(0)
|
||||
).Elif(uart_rx_ev, cnt.eq(cnt + 1)),
|
||||
).Elif(uart.rx_ev, cnt.eq(cnt + 1)),
|
||||
|
||||
sr.eq(Cat(uart.rx_dat, sr[0:24]))
|
||||
]
|
||||
|
||||
# FSM
|
||||
fsm = FSM("IDLE",
|
||||
"GET_BL", "GET_ADDR",
|
||||
"GET_DATA", "WRITE_CSR",
|
||||
"READ_CSR", "SEND_DATA")
|
||||
|
||||
# State done
|
||||
get_bl_done = Signal()
|
||||
|
|
@ -64,13 +67,13 @@ class Uart2Csr(Module):
|
|||
# Idle
|
||||
#
|
||||
fsm.act(fsm.IDLE,
|
||||
If(uart.rx_ev and (uart.rx_dat == WRITE_CMD or uart.rx_dat == READ_CMD),
|
||||
If(uart.rx_ev & ((uart.rx_dat == WRITE_CMD) | (uart.rx_dat == READ_CMD)),
|
||||
fsm.next_state(fsm.GET_BL)
|
||||
)
|
||||
)
|
||||
|
||||
self.sync +=[
|
||||
If(fsm.ongoing(fsm.IDLE) and uart_rx_env,
|
||||
If(fsm.ongoing(fsm.IDLE) & uart.rx_ev,
|
||||
cmd.eq(uart.rx_dat)
|
||||
)
|
||||
|
||||
|
|
@ -85,7 +88,7 @@ class Uart2Csr(Module):
|
|||
)
|
||||
)
|
||||
|
||||
self.comb += get_bl_done.eq(uart_rx_ev and fsm.ongoing(fsm.GET_BL))
|
||||
self.comb += get_bl_done.eq(uart.rx_ev & fsm.ongoing(fsm.GET_BL))
|
||||
|
||||
self.sync +=[
|
||||
If(get_bl_done,
|
||||
|
|
@ -97,19 +100,19 @@ class Uart2Csr(Module):
|
|||
# Get address
|
||||
#
|
||||
fsm.act(fsm.GET_ADDR,
|
||||
If(get_addr_done and cmd == WRITE_CMD,
|
||||
If(get_addr_done & (cmd == WRITE_CMD),
|
||||
fsm.next_state(fsm.GET_DATA)
|
||||
).Elif(get_addr_done and cmd == READ_CMD,
|
||||
).Elif(get_addr_done & (cmd == READ_CMD),
|
||||
fsm.next_state(fsm.READ_CSR)
|
||||
)
|
||||
)
|
||||
|
||||
self.comb += get_addr_done.eq(uart_rx_ev and rx_cnt == 4 and fsm.ongoing(fsm.GET_ADDR))
|
||||
self.comb += get_addr_done.eq(uart.rx_ev & (cnt == 4) & fsm.ongoing(fsm.GET_ADDR))
|
||||
|
||||
self.sync +=[
|
||||
If(get_addr_done,
|
||||
addr.eq(sr)
|
||||
).Elif(write_data_done or send_data_done,
|
||||
).Elif(get_data_done | send_data_done,
|
||||
addr.eq(addr + 4)
|
||||
)
|
||||
]
|
||||
|
|
@ -123,7 +126,7 @@ class Uart2Csr(Module):
|
|||
)
|
||||
)
|
||||
|
||||
self.comb += get_data_done.eq(uart_rx_ev and fsm.ongoing(fsm.GET_DATA))
|
||||
self.comb += get_data_done.eq(uart.rx_ev & fsm.ongoing(fsm.GET_DATA))
|
||||
|
||||
self.sync +=[
|
||||
If(get_data_done,
|
||||
|
|
@ -152,7 +155,7 @@ class Uart2Csr(Module):
|
|||
# Send Data
|
||||
#
|
||||
fsm.act(fsm.SEND_DATA,
|
||||
If(send_data_done and (not burst_cnt),
|
||||
If(send_data_done & (not burst_cnt),
|
||||
fsm.next_state(fsm.IDLE)
|
||||
).Elif(send_data_done,
|
||||
fsm.next_state(fsm.READ_CSR)
|
||||
|
|
@ -160,9 +163,9 @@ class Uart2Csr(Module):
|
|||
)
|
||||
|
||||
self.comb += [
|
||||
uart.tx_dat.eq(csr.dat_r),
|
||||
uart.we.eq(fsm.entering(fsm.SEND_DATA)),
|
||||
send_data_done.eq(~uart.we or uart.tx_ev)
|
||||
uart.tx_dat.eq(self.csr.dat_r),
|
||||
uart.tx_we.eq(fsm.entering(fsm.SEND_DATA)),
|
||||
send_data_done.eq(~uart.tx_we | uart.tx_ev)
|
||||
]
|
||||
|
||||
#
|
||||
|
|
@ -171,7 +174,7 @@ class Uart2Csr(Module):
|
|||
self.sync +=[
|
||||
self.csr.adr.eq(addr),
|
||||
self.csr.dat_w.eq(data),
|
||||
If(fsm.ongoing(fsm.WRITE_CSR,
|
||||
If(fsm.ongoing(fsm.WRITE_CSR),
|
||||
self.csr.we.eq(1)
|
||||
).Else(
|
||||
self.csr.we.eq(0)
|
||||
|
|
|
|||
|
|
@ -28,10 +28,10 @@ class MiIo:
|
|||
comb = []
|
||||
|
||||
if "I" in self.mode:
|
||||
comb += self.ireg.field.w.eq(self.i)
|
||||
comb += [self.ireg.field.w.eq(self.i)]
|
||||
|
||||
if "O" in self.mode:
|
||||
comb += self.o.eq(self.oreg.field.r)
|
||||
comb += [self.o.eq(self.oreg.field.r)]
|
||||
|
||||
return Fragment(comb) + self.bank.get_fragment()
|
||||
#
|
||||
|
|
|
|||
Loading…
Reference in New Issue