soc/cores: add PRBS (Pseudo Random Binary Sequence) Generator/Checker
Imported from LiteICLink. PRBS can be useful for different purposes, so is better integrated in LiteX.
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from operator import xor, add
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from functools import reduce
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from migen import *
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from migen.genlib.cdc import MultiReg
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class PRBSGenerator(Module):
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def __init__(self, n_out, n_state=23, taps=[17, 22]):
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self.o = Signal(n_out)
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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curval += [0]*(n_out - n_state)
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for i in range(n_out):
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nv = reduce(xor, [curval[tap] for tap in taps])
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curval.insert(0, nv)
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curval.pop()
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self.sync += [
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state.eq(Cat(*curval[:n_state])),
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self.o.eq(Cat(*curval))
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]
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class PRBS7Generator(PRBSGenerator):
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def __init__(self, n_out):
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PRBSGenerator.__init__(self, n_out, n_state=7, taps=[5, 6])
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class PRBS15Generator(PRBSGenerator):
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def __init__(self, n_out):
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PRBSGenerator.__init__(self, n_out, n_state=15, taps=[13, 14])
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class PRBS31Generator(PRBSGenerator):
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def __init__(self, n_out):
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PRBSGenerator.__init__(self, n_out, n_state=31, taps=[27, 30])
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class PRBSTX(Module):
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def __init__(self, width, reverse=False):
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self.config = Signal(2)
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self.i = Signal(width)
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self.o = Signal(width)
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# # #
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config = Signal(2)
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# generators
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self.specials += MultiReg(self.config, config)
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prbs7 = PRBS7Generator(width)
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prbs15 = PRBS15Generator(width)
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prbs31 = PRBS31Generator(width)
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self.submodules += prbs7, prbs15, prbs31
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# select
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prbs_data = Signal(width)
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self.comb += \
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If(config == 0b11,
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prbs_data.eq(prbs31.o)
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).Elif(config == 0b10,
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prbs_data.eq(prbs15.o)
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).Else(
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prbs_data.eq(prbs7.o)
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)
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# optional bits reversing
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if reverse:
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new_prbs_data = Signal(width)
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self.comb += new_prbs_data.eq(prbs_data[::-1])
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prbs_data = new_prbs_data
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# prbs / data mux
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self.comb += \
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If(config == 0,
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self.o.eq(self.i)
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).Else(
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self.o.eq(prbs_data)
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)
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class PRBSChecker(Module):
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def __init__(self, n_in, n_state=23, taps=[17, 22]):
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self.i = Signal(n_in)
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self.errors = Signal(n_in)
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# # #
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state = Signal(n_state, reset=1)
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curval = [state[i] for i in range(n_state)]
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for i in reversed(range(n_in)):
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correctv = reduce(xor, [curval[tap] for tap in taps])
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self.sync += self.errors[i].eq(self.i[i] != correctv)
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curval.insert(0, self.i[i])
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curval.pop()
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self.sync += state.eq(Cat(*curval[:n_state]))
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class PRBS7Checker(PRBSChecker):
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def __init__(self, n_out):
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PRBSChecker.__init__(self, n_out, n_state=7, taps=[5, 6])
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class PRBS15Checker(PRBSChecker):
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def __init__(self, n_out):
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PRBSChecker.__init__(self, n_out, n_state=15, taps=[13, 14])
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class PRBS31Checker(PRBSChecker):
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def __init__(self, n_out):
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PRBSChecker.__init__(self, n_out, n_state=31, taps=[27, 30])
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class PRBSRX(Module):
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def __init__(self, width, reverse=False):
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self.i = Signal(width)
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self.config = Signal(2)
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self.errors = Signal(32)
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# # #
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config = Signal(2)
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# optional bits reversing
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prbs_data = self.i
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if reverse:
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new_prbs_data = Signal(width)
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self.comb += new_prbs_data.eq(prbs_data[::-1])
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prbs_data = new_prbs_data
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# checkers
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self.specials += MultiReg(self.config, config)
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prbs7 = PRBS7Checker(width)
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prbs15 = PRBS15Checker(width)
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prbs31 = PRBS31Checker(width)
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self.submodules += prbs7, prbs15, prbs31
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self.comb += [
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prbs7.i.eq(prbs_data),
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prbs15.i.eq(prbs_data),
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prbs31.i.eq(prbs_data)
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]
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# errors count
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self.sync += \
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If(config == 0,
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self.errors.eq(0)
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).Elif(self.errors != (2**32-1),
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If(config == 0b01,
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self.errors.eq(self.errors + (prbs7.errors != 0))
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).Elif(config == 0b10,
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self.errors.eq(self.errors + (prbs15.errors != 0))
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).Elif(config == 0b11,
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self.errors.eq(self.errors + (prbs31.errors != 0))
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)
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)
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