actorlib/spi: fix memory port we/wd

2012-10-04 20:10:24 +02:00 · 2012-10-04 20:10:24 +02:00 · 24877f271b
parent 035870703f
commit 24877f271b
1 changed files with 1 additions and 1 deletions
--- a/migen/actorlib/spi.py
+++ b/migen/actorlib/spi.py
@ -24,7 +24,7 @@ class Collector(Actor):
 		dummy = Signal(BV(self._dw))
 		wd = Signal(BV(self._dw))
 		we = Signal()
-		wp = MemoryPort(wa, dummy, wd, we)
+		wp = MemoryPort(wa, dummy, we, wd)
 		ra = Signal(BV(bits_for(self._depth-1)))
 		rd = Signal(BV(self._dw))
 		rp = MemoryPort(ra, rd)