efinix: add preliminary DDR support (WIP)
This commit is contained in:
Franck Jullien
parent
b9e99f576c
commit
24a920f2d1
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@ -1,3 +1,4 @@
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from litex.build.efinix.programmer import EfinixProgrammer
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from litex.build.efinix.dbparser import EfinixDbParser
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from litex.build.efinix.ifacewriter import InterfaceWriter
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from litex.build.efinix.ddr import EfinixDDR
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@ -0,0 +1,97 @@
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import os
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from migen import *
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from migen.genlib.cdc import *
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from migen import ClockDomain
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from litex.build.generic_platform import *
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from litex.soc.interconnect import axi
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from litex.build import tools
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class EfinixDDR(Module):
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def __init__(self, platform, config):
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self.blocks = []
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self.platform = platform
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self.config = config
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self.nb_ports = 1
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if config['ports'] != None:
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self.nb_ports = self.config['ports']
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self.clock_domains.cd_axi_ddr = ClockDomain()
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self.port0 = port0 = axi.AXIInterface(data_width=256, address_width=32, id_width=8, clock_domain="axi_ddr")
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if self.nb_ports == 2:
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self.port1 = port1 = axi.AXIInterface(data_width=256, address_width=32, id_width=8, clock_domain="axi_ddr")
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axi_clk = platform.add_iface_io('axi_user_clk')
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self.cd_axi_ddr.clk.eq(axi_clk),
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for i in range (0, self.nb_ports):
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ios = [('axi', i,
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Subsignal('wdata', Pins(256)),
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Subsignal('wready', Pins(1)),
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Subsignal('wid', Pins(8)),
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Subsignal('bready', Pins(1)),
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Subsignal('rdata', Pins(256)),
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Subsignal('aid', Pins(8)),
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Subsignal('bvalid', Pins(1)),
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Subsignal('rlast', Pins(1)),
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Subsignal('bid', Pins(8)),
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Subsignal('asize', Pins(3)),
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Subsignal('atype', Pins(1)),
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Subsignal('aburst', Pins(2)),
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Subsignal('wvalid', Pins(1)),
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Subsignal('aaddr', Pins(32)),
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Subsignal('rid', Pins(8)),
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Subsignal('avalid', Pins(1)),
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Subsignal('rvalid', Pins(1)),
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Subsignal('alock', Pins(2)),
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Subsignal('rready', Pins(1)),
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Subsignal('rresp', Pins(2)),
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Subsignal('wstrb', Pins(32)),
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Subsignal('aready', Pins(1)),
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Subsignal('alen', Pins(8)),
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Subsignal('wlast', Pins(1)),
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)]
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io = platform.add_iface_ios(ios)
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port = port0
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if i == 0:
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port = port1
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is_read = port.ar.valid
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self.comb += [io.aaddr.eq(Mux(is_read, port.ar.addr, port.aw.addr)),
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io.aid.eq(Mux(is_read, port.ar.id, port.aw.id)),
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io.alen.eq(Mux(is_read, port.ar.len, port.aw.len)),
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io.asize.eq(Mux(is_read, port.ar.size[0:4], port.aw.size[0:4])), #TODO: check
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io.aburst.eq(Mux(is_read, port.ar.burst, port.aw.burst)),
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io.alock.eq(Mux(is_read, port.ar.lock, port.aw.lock)),
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io.avalid.eq(Mux(is_read, port.ar.valid, port.aw.valid)),
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io.atype.eq(~is_read),
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port.aw.ready.eq(io.aready),
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port.ar.ready.eq(io.aready),
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io.wid.eq(port.w.id),
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io.wstrb.eq(port.w.strb),
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io.wdata.eq(port.w.data),
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io.wlast.eq(port.w.last),
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io.wvalid.eq(port.w.valid),
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port.w.ready.eq(io.wready),
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port.r.id.eq(io.rid),
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port.r.data.eq(io.rdata),
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port.r.last.eq(io.rlast),
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port.r.resp.eq(io.rresp),
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port.r.valid.eq(io.rvalid),
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io.rready.eq(port.r.ready),
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port.b.id.eq(io.bid),
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port.b.valid.eq(io.bvalid),
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io.bready.eq(port.b.ready),
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# port.b.resp ??
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]
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@ -188,6 +188,7 @@ def _build_peri(efinity_path, build_name, partnumber, named_sc, named_pc, fragme
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header = platform.toolchain.ifacewriter.header(build_name, partnumber)
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gen = platform.toolchain.ifacewriter.generate()
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#TODO: move this to ifacewriter
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gpio = _build_iface_gpio(named_sc, named_pc, fragment, platform, specials_gpios)
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add = '\n'.join(additional_iface_commands)
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footer = platform.toolchain.ifacewriter.footer()
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@ -274,7 +275,7 @@ class EfinityToolchain():
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self.efinity_path = efinity_path
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self.additional_sdc_commands = []
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self.additional_xml_commands = []
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self.ifacewriter = InterfaceWriter("iface.py", efinity_path)
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self.ifacewriter = InterfaceWriter(efinity_path)
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self.specials_gpios = []
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self.additional_iface_commands = []
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@ -338,6 +339,10 @@ class EfinityToolchain():
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additional_iface_commands = self.additional_iface_commands,
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specials_gpios = self.specials_gpios)
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# DDR doesn't have Python API so we need to configure it
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# directly in the peri.xml file
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self.ifacewriter.add_ddr_xml(build_name)
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# Run
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if run:
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subprocess.call([self.efinity_path + '/scripts/efx_run.py', build_name + '.xml', '-f', 'compile'])
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@ -1,12 +1,120 @@
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import os
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import csv
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import re
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import datetime
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from xml.dom import expatbuilder
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import xml.etree.ElementTree as et
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from litex.build import tools
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namespaces = { 'efxpt' : 'http://www.efinixinc.com/peri_design_db',
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'xi' : 'http://www.w3.org/2001/XInclude'
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}
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class InterfaceWriter():
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def __init__(self, filename, efinity_path):
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self.file = filename
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def __init__(self, efinity_path):
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self.efinity_path = efinity_path
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self.blocks = []
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def add_ddr_xml(self, filename):
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et.register_namespace('efxpt', "http://www.efinixinc.com/peri_design_db")
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tree = et.parse(filename + '.peri.xml')
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root = tree.getroot()
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ddr_info = root.find('efxpt:ddr_info', namespaces)
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et.SubElement(ddr_info, 'efxpt:ddr',
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name = 'ddr_inst1',
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ddr_def = 'DDR_0',
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cs_preset_id = '173',
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cs_mem_type = 'LPDDR3',
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cs_ctrl_width = 'x32',
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cs_dram_width = 'x32',
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cs_dram_density = '8G',
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cs_speedbin = '800',
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target0_enable = 'true',
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target1_enable = 'false',
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ctrl_type = 'none')
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axi_suffix = '' # '_1' for second port
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type_suffix = '_0' # '_1' for second port
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gen_pin_target0 = et.SubElement(ddr_info, 'efxpt:gen_pin_target0')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wdata{}'.format(axi_suffix), type_name='WDATA{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wready{}'.format(axi_suffix), type_name='WREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wid{}'.format(axi_suffix), type_name='WID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_bready{}'.format(axi_suffix), type_name='BREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_rdata{}'.format(axi_suffix), type_name='RDATA{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_aid{}'.format(axi_suffix), type_name='AID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_bvalid{}'.format(axi_suffix), type_name='BVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_rlast{}'.format(axi_suffix), type_name='RLAST{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_bid{}'.format(axi_suffix), type_name='BID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_asize{}'.format(axi_suffix), type_name='ASIZE{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_atype{}'.format(axi_suffix), type_name='ATYPE{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_aburst{}'.format(axi_suffix), type_name='ABURST{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wvalid{}'.format(axi_suffix), type_name='WVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wlast{}'.format(axi_suffix), type_name='WLAST{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_aaddr{}'.format(axi_suffix), type_name='AADDR{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_rid{}'.format(axi_suffix), type_name='RID{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_avalid{}'.format(axi_suffix), type_name='AVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_rvalid{}'.format(axi_suffix), type_name='RVALID{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_alock{}'.format(axi_suffix), type_name='ALOCK{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_rready{}'.format(axi_suffix), type_name='RREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_rresp{}'.format(axi_suffix), type_name='RRESP{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_wstrb{}'.format(axi_suffix), type_name='WSTRB{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_aready{}'.format(axi_suffix), type_name='AREADY{}'.format(type_suffix), is_bus = 'false')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_alen{}'.format(axi_suffix), type_name='ALEN{}'.format(type_suffix), is_bus = 'true')
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et.SubElement(gen_pin_target0, 'efxpt:pin', name='axi_clk', type_name='ACLK_0', is_bus = 'false', is_clk = 'true', is_clk_invert = 'false')
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gen_pin_config = et.SubElement(ddr_info, 'efxpt:gen_pin_config')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SEQ_RST', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SCL_IN', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SEQ_START', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='RSTN', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SDA_IN', is_bus = 'false')
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et.SubElement(gen_pin_config, 'efxpt:pin', name='', type_name='CFG_SDA_OEN', is_bus = 'false')
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cs_fpga = et.SubElement(ddr_info, 'efxpt:cs_fpga')
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et.SubElement(cs_fpga, 'efxpt:param', name='FPGA_ITERM', value='120', value_type = 'str')
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et.SubElement(cs_fpga, 'efxpt:param', name='FPGA_OTERM', value='34', value_type = 'str')
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cs_memory = et.SubElement(ddr_info, 'efxpt:cs_memory')
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et.SubElement(cs_memory, 'efxpt:param', name='RTT_NOM', value='RZQ/2', value_type = 'str')
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et.SubElement(cs_memory, 'efxpt:param', name='MEM_OTERM', value='40', value_type = 'str')
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et.SubElement(cs_memory, 'efxpt:param', name='CL', value='RL=6/WL=3', value_type = 'str')
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timing = et.SubElement(ddr_info, 'efxpt:cs_memory_timing')
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et.SubElement(timing, 'efxpt:param', name='tRAS', value= '42.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRC', value= '60.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRP', value= '18.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRCD', value= '18.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tREFI', value= '3.900', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRFC', value= '210.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRTP', value= '10.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tWTR', value= '10.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tRRD', value= '10.000', value_type='float')
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et.SubElement(timing, 'efxpt:param', name='tFAW', value= '50.000', value_type='float')
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cs_control = et.SubElement(ddr_info, 'efxpt:cs_control')
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et.SubElement(cs_control, 'efxpt:param', name='AMAP', value= 'ROW-COL_HIGH-BANK-COL_LOW', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='EN_AUTO_PWR_DN', value= 'Off', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='EN_AUTO_SELF_REF', value= 'No', value_type='str')
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cs_gate_delay = et.SubElement(ddr_info, 'efxpt:cs_gate_delay')
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et.SubElement(cs_control, 'efxpt:param', name='EN_DLY_OVR', value= 'No', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='GATE_C_DLY', value= '3', value_type='str')
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et.SubElement(cs_control, 'efxpt:param', name='GATE_F_DLY', value= '0', value_type='str')
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xml_string = et.tostring(root, 'utf-8')
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reparsed = expatbuilder.parseString(xml_string, False)
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print_string = reparsed.toprettyxml(indent=" ")
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# Remove lines with only whitespaces. Not sure why they are here
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print_string = os.linesep.join([s for s in print_string.splitlines() if s.strip()])
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tools.write_to_file("{}.peri.xml".format(filename), print_string)
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def header(self, build_name, partnumber):
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header = "# Autogenerated by LiteX / git: " + tools.get_litex_git_revision()
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header += """
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@ -93,7 +201,7 @@ design.create('{2}', '{3}', './../build', overwrite=True)
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def footer(self):
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return """
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# Check design, generate constraints and reports
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design.generate(enable_bitstream=True)
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#design.generate(enable_bitstream=True)
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# Save the configured periphery design
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design.save()"""
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@ -74,3 +74,10 @@ class EfinixPlatform(GenericPlatform):
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# We don't want this IO to be in the interface configuration file as a simple GPIO
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self.toolchain.specials_gpios.append(tmp)
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return tmp
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def add_iface_ios(self, io):
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self.add_extension(io)
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tmp = self.request(io[0][0])
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for s in tmp.flatten():
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self.toolchain.specials_gpios.append(s)
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return tmp
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@ -79,11 +79,12 @@ class TRIONPLL(Module):
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self.logger.info("Using {}".format(pll_res))
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self.logger.info("Clock source: {}, using EXT_CLK{}".format(block['input_clock'], clock_no))
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=True):
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def create_clkout(self, cd, freq, phase=0, margin=1e-2, with_reset=False, user_clk=True):
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assert self.nclkouts < self.nclkouts_max
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clk_out_name = '{}_CLKOUT{}'.format(self.pll_name, self.nclkouts)
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if user_clk == True:
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self.platform.add_extension([(clk_out_name, 0, Pins(1))])
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tmp = self.platform.request(clk_out_name)
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@ -94,6 +95,7 @@ class TRIONPLL(Module):
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self.platform.toolchain.specials_gpios.append(tmp)
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self.comb += cd.clk.eq(tmp)
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create_clkout_log(self.logger, cd.name, freq, margin, self.nclkouts)
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self.nclkouts += 1
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block = self.platform.toolchain.ifacewriter.get_block(self.pll_name)
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