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litex_sim: use flash model in simulation

This commit is contained in:
Piotr Binkowski 2021-08-27 16:38:43 +02:00 committed by Pawel Sagan
parent 837de615e6
commit 25e0153dd5
1 changed files with 7 additions and 3 deletions
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10
litex/tools/litex_sim.py
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@ -116,6 +116,7 @@ class SimSoC(SoCCore):
with_i2c = False, with_i2c = False,
with_sdcard = False, with_sdcard = False,
with_spi_flash = False, with_spi_flash = False,
flash_init = [],
sim_debug = False, sim_debug = False,
trace_reset_on = False, trace_reset_on = False,
**kwargs): **kwargs):
@ -253,9 +254,10 @@ class SimSoC(SoCCore):
if with_spi_flash: if with_spi_flash:
from litespi.modules import S25FL128L from litespi.modules import S25FL128L
from litespi.opcodes import SpiNorFlashOpCodes as Codes from litespi.opcodes import SpiNorFlashOpCodes as Codes
platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/iddr_verilog.v") if flash_init is None:
platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/oddr_verilog.v") platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/iddr_verilog.v")
self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True) platform.add_sources(os.path.abspath(os.path.dirname(__file__)), "../build/sim/verilog/oddr_verilog.v")
self.add_spi_flash(mode="4x", module=S25FL128L(Codes.READ_1_1_4), with_master=True, init=flash_init)
# Simulation debugging ---------------------------------------------------------------------- # Simulation debugging ----------------------------------------------------------------------
if sim_debug: if sim_debug:
@ -321,6 +323,7 @@ def sim_args(parser):
parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support") parser.add_argument("--with-i2c", action="store_true", help="Enable I2C support")
parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support") parser.add_argument("--with-sdcard", action="store_true", help="Enable SDCard support")
parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)") parser.add_argument("--with-spi-flash", action="store_true", help="Enable SPI Flash (MMAPed)")
parser.add_argument("--flash-init", default=None, help="Flash init file")
parser.add_argument("--trace", action="store_true", help="Enable Tracing") parser.add_argument("--trace", action="store_true", help="Enable Tracing")
parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)") parser.add_argument("--trace-fst", action="store_true", help="Enable FST tracing (default=VCD)")
parser.add_argument("--trace-start", default="0", help="Time to start tracing (ps)") parser.add_argument("--trace-start", default="0", help="Time to start tracing (ps)")
@ -384,6 +387,7 @@ def main():
sim_debug = args.sim_debug, sim_debug = args.sim_debug,
trace_reset_on = trace_start > 0 or trace_end > 0, trace_reset_on = trace_start > 0 or trace_end > 0,
sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness), sdram_init = [] if args.sdram_init is None else get_mem_data(args.sdram_init, cpu.endianness),
flash_init = None if args.flash_init is None else get_mem_data(args.flash_init, "big"),
**soc_kwargs) **soc_kwargs)
if args.ram_init is not None or args.sdram_init is not None: if args.ram_init is not None or args.sdram_init is not None:
soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"]) soc.add_constant("ROM_BOOT_ADDRESS", soc.mem_map["main_ram"])