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Merge pull request #1288 from fjullien/hyperram_timeout 

Hyperram timeout and cyc
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enjoy-digital 2022-05-02 16:30:58 +02:00 committed by GitHub
parent c12bdf5454 a66af6343e
commit 25e7569cd1
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1 changed files with 28 additions and 4 deletions
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32
litex/soc/cores/hyperbus.py
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@ -24,7 +24,7 @@ class HyperRAM(Module):
This core favors portability and ease of use over performance. This core favors portability and ease of use over performance.
""" """
def __init__(self, pads, latency=6): def __init__(self, frequency, pads, latency=6, Tcsm=4e-6):
self.pads = pads self.pads = pads
self.bus = bus = wishbone.Interface() self.bus = bus = wishbone.Interface()
@ -61,6 +61,25 @@ class HyperRAM(Module):
else: else:
self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n) self.specials += DifferentialOutput(clk, pads.clk_p, pads.clk_n)
# Timeout counter --------------------------------------------------------------------------
timeout_value = int(Tcsm * frequency)
timeout_cnt = Signal(32)
timeout_rst = Signal()
timeout = Signal()
self.sync += [
If(timeout_rst,
timeout_cnt.eq(0),
timeout.eq(0)
).Else(
If(timeout_cnt < timeout_value,
timeout_cnt.eq(timeout_cnt + 1)
).Else(
timeout.eq(1)
)
),
]
# Clock Generation (sys_clk/4) ------------------------------------------------------------- # Clock Generation (sys_clk/4) -------------------------------------------------------------
self.sync += clk_phase.eq(clk_phase + 1) self.sync += clk_phase.eq(clk_phase + 1)
cases = {} cases = {}
@ -122,6 +141,7 @@ class HyperRAM(Module):
first = Signal() first = Signal()
self.submodules.fsm = fsm = FSM(reset_state="IDLE") self.submodules.fsm = fsm = FSM(reset_state="IDLE")
fsm.act("IDLE", fsm.act("IDLE",
timeout_rst.eq(1),
NextValue(first, 1), NextValue(first, 1),
If(bus.cyc & bus.stb, If(bus.cyc & bus.stb,
If(clk_phase == 0, If(clk_phase == 0,
@ -139,7 +159,9 @@ class HyperRAM(Module):
# Wait for 6*2 cycles... # Wait for 6*2 cycles...
If(cycles == (6*2 - 1), If(cycles == (6*2 - 1),
NextState("WAIT-LATENCY") NextState("WAIT-LATENCY")
) ),
# Always check if bus cycle is still active
If(~bus.cyc, NextState("IDLE"))
) )
fsm.act("WAIT-LATENCY", fsm.act("WAIT-LATENCY",
# Set CSn. # Set CSn.
@ -151,7 +173,9 @@ class HyperRAM(Module):
# Early Write Ack (to allow bursting). # Early Write Ack (to allow bursting).
bus.ack.eq(bus.we), bus.ack.eq(bus.we),
NextState("READ-WRITE-DATA0") NextState("READ-WRITE-DATA0")
) ),
# Always check if bus cycle is still active
If(~bus.cyc, NextState("IDLE"))
) )
states = {8:4, 16:2}[dw] states = {8:4, 16:2}[dw]
for n in range(states): for n in range(states):
@ -172,7 +196,7 @@ class HyperRAM(Module):
If(n == (states - 1), If(n == (states - 1),
NextValue(first, 0), NextValue(first, 0),
# Continue burst when a consecutive access is ready. # Continue burst when a consecutive access is ready.
If(bus.stb & bus.cyc & (bus.we == bus_we) & (bus.adr == (bus_adr + 1)), If(bus.stb & bus.cyc & (bus.we == bus_we) & (bus.adr == (bus_adr + 1)) & ~timeout,
# Latch Bus. # Latch Bus.
bus_latch.eq(1), bus_latch.eq(1),
# Early Write Ack (to allow bursting). # Early Write Ack (to allow bursting).