cores/dma/WishboneDMAReader: Add FIFO to pipeline reads and allow burst on Wishbone.

This commit is contained in:
Florent Kermarrec 2023-01-09 21:33:59 +01:00
parent 0440733fc0
commit 25ea4a07ae
1 changed files with 18 additions and 19 deletions

View File

@ -39,7 +39,7 @@ class WishboneDMAReader(Module, AutoCSR):
source : Record("data") source : Record("data")
Source for MMAP word results from reading. Source for MMAP word results from reading.
""" """
def __init__(self, bus, endianness="little", with_csr=False): def __init__(self, bus, endianness="little", fifo_depth=16, with_csr=False):
assert isinstance(bus, wishbone.Interface) assert isinstance(bus, wishbone.Interface)
self.bus = bus self.bus = bus
self.sink = sink = stream.Endpoint([("address", bus.adr_width, ("last", 1))]) self.sink = sink = stream.Endpoint([("address", bus.adr_width, ("last", 1))])
@ -47,30 +47,28 @@ class WishboneDMAReader(Module, AutoCSR):
# # # # # #
data = Signal(bus.data_width) # FIFO..
self.submodules.fifo = fifo = stream.SyncFIFO([("data", bus.data_width)], depth=fifo_depth)
self.submodules.fsm = fsm = FSM(reset_state="BUS-READ") # Reads -> FIFO.
fsm.act("BUS-READ", self.comb += [
bus.stb.eq(sink.valid), bus.stb.eq(sink.valid & fifo.sink.ready),
bus.cyc.eq(sink.valid), bus.cyc.eq(sink.valid & fifo.sink.ready),
bus.we.eq(0), bus.we.eq(0),
bus.sel.eq(2**(bus.data_width//8)-1), bus.sel.eq(2**(bus.data_width//8)-1),
bus.adr.eq(sink.address), bus.adr.eq(sink.address),
fifo.sink.last.eq(sink.last),
fifo.sink.data.eq(bus.dat_r),
If(bus.stb & bus.ack, If(bus.stb & bus.ack,
NextValue(data, format_bytes(bus.dat_r, endianness)),
NextState("SOURCE-WRITE")
)
)
fsm.act("SOURCE-WRITE",
source.valid.eq(1),
source.last.eq(sink.last),
source.data.eq(data),
If(source.ready,
sink.ready.eq(1), sink.ready.eq(1),
NextState("BUS-READ") fifo.sink.valid.eq(1),
) ),
) ]
# FIFO -> Output.
self.comb += fifo.source.connect(source)
# CSRs.
if with_csr: if with_csr:
self.add_csr() self.add_csr()
@ -140,8 +138,8 @@ class WishboneDMAWriter(Module, AutoCSR):
# # # # # #
# Writes.
data = Signal(bus.data_width) data = Signal(bus.data_width)
self.comb += [ self.comb += [
bus.stb.eq(sink.valid), bus.stb.eq(sink.valid),
bus.cyc.eq(sink.valid), bus.cyc.eq(sink.valid),
@ -152,6 +150,7 @@ class WishboneDMAWriter(Module, AutoCSR):
sink.ready.eq(bus.ack), sink.ready.eq(bus.ack),
] ]
# CSRs.
if with_csr: if with_csr:
self.add_csr() self.add_csr()